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MT88E39AS1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
MT88E39 Data Sheet
13
Zarlink Semiconductor Inc.
Figure 10 - Input and Output Timing (Bellcore CND Service)
Figure 11 - Serial Data Interface Timing (Mode 0)
First Ring
Input FSK
Data
Second
Ring
2 sec
channel seizure
Mark state
checksum
TIP/RING
PWDN
OSC2
CD
*
DATA
DCLK
DR
*
High (Input Idle)
t
PU
500 ms
(min)
t
IAL
200 ms
(min)
t
PD
t
IAH
High (Input Idle)
* with pull-up resistor in mode 0
(mode 0)
TIP/RING
DATA
DCLK
DR
*
stop
start
stop
start
stop
start
stop
start
b0 b1 b2 b3 b4 b5
b6
b7
b7
10
b0 b1 b2 b3 b4 b5
b6
b7
10
b0 b1 b2
10
b7 b0 b1 b2 b3 b4 b5
b6
b7 b0 b1 b2 b3 b4 b5
b6
b7
b0 b1 b2
stop
start
stop
start
t
IDD
t
CRD
* with external pull-up resistor
MT88E39 Data Sheet
14
Zarlink Semiconductor Inc.
Figure 12 - Serial Data Interface Timing (Mode 1)
DCLK clears DR
stop
start
stop
0
1
234
5
67
7
word N
word N+1
0 1 2 3 4 5 67
word N
0
word N-1
7
1/f
DCLK1
t
RL
t
DDH
6
t
DDS
Demodulated
DR
(Data Ready)
DCLK (Data Clock)*
DATA Output
Data
(Internal Signal)
¡
DCLK does not clear DR, so DR is low for maximum time (1/2 bit time)
CMOS
Output
Schmitt Input
¡
The DCLK input must be low before and after DR
falling edge
*
¿
¿
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

MT88E39AS1

Mfr. #:
Buy MT88E39AS1
Manufacturer:
Microchip / Microsemi
Description:
Telecom Interface ICs Pb Free CNIC 1.1
Lifecycle:
New from this manufacturer.
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