DS1848
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2-WIRE OPERATION
Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor or device.
Data on the SDA pin may only change during SCL low time periods. Data changes during SCL high
periods will indicate a start or stop conditions depending on the conditions discussed below. Refer to the
timing diagram (Figure 4) for further details.
Start Condition: A high-to-low transition of SDA with SCL high is a start condition that must precede
any other command. Refer to the timing diagram (Figure 4) for further details.
Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition. After a read
sequence, the stop command places the DS1848 into a low-power mode. Refer to the timing diagram
(Figure 4) for further details.
Acknowledge: All address and data byte are transmitted via a serial protocol. The DS1848 pulls the SDA
line low during the ninth clock pulse to acknowledge that it has received each word.
Standby Mode: The DS1848 features a low-power mode that is automatically enabled after power-on,
after a stop command, and after the completion of all internal operations.
2-Wire Interface Reset: After any interruption in protocol, power loss, or system reset, the following
steps reset the DS1848.
1. Clock up to nine cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a START condition while SDA is high.
Device Addressing: The DS1848 must receive an 8-bit device address word following a START
condition to enable a specific device for a read or write operation. The address word is clocked into the
DS1848 MSB to LSB. The address word consists of Ah (10106) followed by A2, A1, and A0 then the
R/W bit. If the R/W bit is high, a read operation is initiated. If the R/W is low, a write operation is
initiated. For a device to become active, the values of A2, A1 and A0 must be the same as the hard-wired
address pins on the DS1848. Upon a match of written and hard-wired addresses, the DS1848 will output a
zero for one clock cycle as an acknowledge. If the address does not match, the DS1848 returns to a low-
power mode.
Write Operations: After receiving a matching address byte with the R/W bit set low, the device goes
into the write mode of operation. The master must transmit an 8-bit EEPROM memory address to the
device to define the address where the data is to be written. After byte has been received, the DS1848 will
transmit a zero for one clock cycle to acknowledge the receipt of the address. The master must then
transmit an 8-bit data word to be written into this address. The DS1848 will again transmit a zero for one
clock cycle to acknowledge the receipt of the data. At this point, the master must terminate the write
operation with a STOP condition. The DS1848 then enters an internally timed write process t
w
to the
EEPROM memory. All inputs are disabled during this byte write cycle.
The DS1848 is capable of an 8-byte page write. A page write is initiated the same way as a byte write, but
the master does not send a STOP condition after the first byte. Instead, after the slave acknowledges
receipt of the data byte, the master can send up to seven more bytes using the same nine-clock sequence.
