FEMTOCLOCKS™ Crystal-to-LVCMOS/
LVTTL Frequency Synthesizer
840002
DATASHEET
840002 REVISION C NOVEMBER 10, 2014 1 ©2014 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 840002 is a 2 output LVCMOS/LVTTL Synthesizer optimized
to generate Fibre Channel reference clock frequencies. Using a
26.5625MHz, 18pF parallel resonant crystal, the following frequencies
can be generated based on the 2 frequency select pins (F_SEL1:0):
212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and 53.125MHz.
The 840002 uses low phase noise VCO technology and can achieve
1ps or lower typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The 840002 is packaged in a 16-pin TSSOP package.
BLOCK DIAGRAM PIN ASSIGNMENT
F_SEL0
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
V
DDA
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
F_SEL1
GND
GND
Q0
Q1
V
DDO
XTAL_IN
XTAL_OUT
840002
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
FEATURES
Two LVCMOS outputs @ 3.3V, 17Ω typical output imped-
ance
Selectable crystal oscillator interface
or LVCMOS single-ended input
Output frequency range: 46.66MHz - 233.33MHz
VCO range: 560MHz - 700MHz
Supports the following output frequencies: 212.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz
RMS phase jitter @ 212.5MHz (637kHz - 10MHz):
0.83ps (typical)
Typical phase noise at 212.5MHz:
Offset Noise Power
100Hz ................-91.3 dBc/Hz
1kHz ..............-114.3 dBc/Hz
10kHz ..............-120.7 dBc/Hz
100kHz ..............-120.2 dBc/Hz
Full 3.3V or 3.3V core/2.5V output supply modes
0°C to 70°C ambient operating temperature
Available in lead-free RoHS compliant package
Q0
Q1
OE
F_SEL1:0
nPLL_SEL
nXTAL_SEL
XTAL_IN
XTAL_OUT
TEST_CLK
MR
OSC
Phase
Detector
VCO
M = ÷24 (fixed)
F_SEL1:0
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
(default)
0
1
1
0
2
N
26.5625MHz
Pullup
Pulldown
Pulldown
Pulldown
Pullup:Pullup
Pulldown
FREQUENCY SELECT FUNCTION TABLE FOR FIBRE CHANNEL APPLICATIONS
Input Frequency
(MHz)
Inputs
Output Frequency
(MHz)
F_SEL1 F_SEL0 M Divider Value N Divider Value M/N Ratio Value
26.5625 0 0 24 3 8 212.5
26.5625 0 1 24 4 6 159.375
26.5625 1 0 24 6 4 106.25
26.5625 1 1 24 12 2 53.125
26.04166 0 1 24 4 6 156.25
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840002 DATA SHEET
2 REVISION C 11/10/14
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
TABLE 3. FREQUENCY SELECT FUNCTION TABLE
Number Name Type Description
1 F_SEL0 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
2 nXTAL_SEL Input Pulldown
Selects between the crystal or TEST_CLK inputs as the PLL reference
source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
3 TEST_CLK Input Pulldown Single-ended LVCMOS/LVTTL clock input.
4 OE Input Pullup
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
5 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing active outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
6 nPLL_SEL Input Pulldown
PLL Bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency = reference
clock frequency/n output divider.
LVCMOS/LVTTL interface levels.
7V
DDA
Power Analog supply pin.
8V
DD
Power Core supply pin.
9,
10
XTAL_OUT,
XTAL_IN
Input Crystal oscillator interface.
11 V
DDO
Power Output supply pin.
12, 13 Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.
14, 15 GND Power Power supply ground.
16 F_SEL1 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Input Frequency
(MHz)
Inputs
Output Frequency
(MHz)
F_SEL1 F_SEL0 M Divider Value N Divider Value M/N Divider Value
26.5625 0 0 24 3 8 212.5
26.5625 0 1 24 4 6 159.375
26.5625 1 0 24 6 4 106.25
26.5625 1 1 24 12 2 53.125
26.04166 0 1 24 4 6 156.25
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
C
PD
Power Dissipation Capacitance 8 pF
R
PULLUP
Input Pullup Resistor 51 kΩ
R
PULLDOWN
Input Pulldown Resistor 51 kΩ
R
OUT
Output Impedance
3.3V±5% 14 17 21 Ω
2.5V±5% 16 21 25 Ω
REVISION C 11/10/14
840002 DATA SHEET
3 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance, θ
JA
89°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDA
Analog Supply Voltage 3.135 3.3 3.465 V
V
DDO
Output Supply Voltage
3.135 3.3 3.465 V
2.375 2.5 2.625 V
I
DD
Power Supply Current 100 mA
I
DDA
Analog Supply Current 12 mA
I
DDO
Output Supply Current 5mA
TABLE 5. CRYSTAL CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input
High Voltage
F_SEL1:0, nPLL_SEL,
nXTAL_SEL, OE, MR
2V
DD
+ 0.3 V
TEST_CLK 2 V
DD
+ 0.3 V
V
IL
Input
Low Voltage
F_SEL1:0, nPLL_SEL,
nXTAL_SEL, OE, MR
-0.3 0.8 V
TEST_CLK -0.3 1.3 V
I
IH
Input
High Current
OE, F_SEL0, F_SEL1 V
DD
= V
IN
= 3.465V 5 µA
nPLL_SEL, MR, nXTAL_
SEL, TEST_CLK
V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input
Low Current
OE, F_SEL0, F_SEL1 V
DD
= 3.465V, V
IN
= 0V -150 µA
nPLL_SEL, MR, nXTAL_
SEL, TEST_CLK
V
DD
= 3.465V, V
IN
= 0V -5 µA
V
OH
Output High Voltage; NOTE 1
V
DDO
= 3.3V ± 5% 2.6 V
V
DDO
= 2.5V ± 5% 1.8 V
V
OL
Output Low Voltage; NOTE 1 V
DDO
= 3.3V or 2.5V ± 5% 0.5 V
NOTE 1: Outputs terminated with 50W to V
DDO
/2. See Parameter Measurement Information, Output Load Test Circuit.
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 26.5625 MHz
Equivalent Series Resistance (ESR) 50 Ω
Shunt Capacitance 7pF
Drive Level 1mW
NOTE: Characterized using an 18pf parallel resonant crystal.

840002AGLFT

Mfr. #:
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner 2 LVCMOS OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
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