REVISION C 11/10/14
840002 DATA SHEET
7 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 840002 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and
V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each V
DDA
.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
DDA
10μF
.01μF
3.3V
.01μF
V
DD
CRYSTAL INPUT INTERFACE
The 840002 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
Figure 2. CRYSTAL INPUt INTERFACE
determined using a 26.5625MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
840002
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840002 DATA SHEET
8 REVISION C 11/10/14
LAYOUT GUIDELINE
Figure 3 shows a schematic example of the 840002. An example
of LVCMOS termination is shown in this schematic. Additional
LVCMOS termination approaches are shown in the LVCMOS
Termination Application Note. In this example, an 18 pF par-
allel resonant 26.5625MHz crystal is used. The C1=22pF and
FIGURE 3. 840002 SCHEMATIC EXAMPLE
C2=22pF are recommended for frequency accuracy. For differ-
ent board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. 1KΩ pullup or pulldown resistors
can be used for the logic control input pins.
To Logic
Input
pins
RU2
Not Install
C2
22pF
VDD
VDD
RD2
1K
LVCMOS
C5
0.1u
RU1
1K
Zo = 50 Ohm
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
C1
22pF
Set Logic
Input to
'0'
VDDA
VDD
U1
ICS840002
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
FSEL0
XTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
VDD XTAL_OUT
XTAL _I N
VDDO
Q1
Q0
GND
GND
FSEL1
Logic Control Input Examples
Optional Termination
RD1
Not Install
X1
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
C4
0.01u
Set Logic
Input to
'1'
C3
10uF
R4
100
VDD
XTAL 2
To Logic
Input
pins
XTAL 1
R2
33
R3
100
R1
10
C6
0.1u
Zo = 50 Ohm
VDD
LVCMOS
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left fl oating. Though
not required, but for additional protection, a 1kΩ resistor can be
tied from XTAL_IN to ground.
TEST_CLK I
NPUT:
For applications not requiring the use of the test clock, it can be
left fl oating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the TEST_CLK to ground.
LVCMOS C
ONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left fl oating. We recommend
that there is no trace attached.
REVISION C 11/10/14
840002 DATA SHEET
9 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for 840002 is: 3085
TABLE 7. θ
JA
VS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 118.2°C/W 106.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 89.0°C/W 81.8°C/W 78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

840002AGLFT

Mfr. #:
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner 2 LVCMOS OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
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