MAX4589EWP Datasheet MAX4589CAP+T, MAX4589CAP, MAX4589EPP | P13-P15

MAX4589

Low-Voltage, High-Isolation,

Dual 2-Channel RF/Video Multiplexer

______________________________________________________________________________________ 13

_______________Detailed Description

Logic-Level Translators

The MAX4589 is constructed of high-frequency “T”

switches, as shown in Figure 8. The logic-level inputs

are translated by amplifier A1 into a V+ to V- logic sig-

nal that drives the internal control logic. The internal

control logic drives the gates of N-channel MOSFETs

N1 and N2 from V+ to V-, turning them fully on or off.

The same signal drives inverter A2 (which drives the P-

channel MOSFETs P1 and P2, turning them fully on or

off) from V+ to V-, and turns the N-channel MOSFET N3

on and off. The logic-level threshold is determined by

and GND.

Switch On Condition

When the switch is on, MOSFETs N1, N2, P1, and P2

are on and MOSFET N3 is off (Figure 8). The signal

path is COM_ to NO_, and because both N-channel

and P-channel MOSFETs act as pure resistances, it is

symmetrical (i.e., signals pass in either direction). The

off MOSFET, N3, has no DC conduction, but has a

small amount of capacitance to GND. The MAX4589’s

construction allows an exceptional 200MHz -3dB band-

width.

Frequency response in 75Ω systems is reasonably flat

up to 50MHz, with typically 2.5dB of insertion loss.

Higher-impedance circuits show even lower attenuation

(and vice versa), but slightly lower bandwidth due to

the increased effect of the internal and external capaci-

tance and the switch’s on-resistance.

The MAX4589 is optimized for ±5V operation. Using

lower supply voltages or a single supply increases

switching time, on-resistance (and therefore on-state

attenuation), and nonlinearity.

Switch Off Condition

When the switch is off, MOSFETs N1, N2, P1, and P2

are off and MOSFET N3 is on (Figure 8). The signal

path is through the parasitic off-capacitances of N1,

N2, P1, and P2, but it is shunted to ground by N3. This

forms a highpass filter whose exact characteristics are

dependent on the source and load impedances. In 75Ω

systems, and below 1MHz, the attenuation exceeds

80dB. This value decreases with increasing frequency

and increasing circuit impedances. External capaci-

tance and board layout dominate overall performance.

CSS

SCLK

DIN A0 A1 BIT 3 DISABLE

DOUT

NOTE: ALL INPUT SIGNALS ARE SPECIFIED WITH t

AND t

< 10ns.

TIMING IS MEASURED FROM 50% OF DIGITAL SIGNAL.

CSH

MAX4589

Figure 7. Serial Timing Diagram

MAX4589

Low-Voltage, High-Isolation,

Dual 2-Channel RF/Video Multiplexer

14 ______________________________________________________________________________________

COM_

NO_

CONTROL

LOGIC

V+

GND

V-

Figure 8. T-Switch Construction

__________Applications Information

Power-Supply Considerations

Overview

The MAX4589 construction is typical of many CMOS

analog switches. It has four supply pins: V+, V-, V

, and

GND. V+ and V- are used to drive the internal CMOS

switches and set the limits of the analog voltage on any

switch. Reverse ESD-protection diodes are internally

connected between each analog signal pin and both

V+ and V-. If the voltage on any pin exceeds V+ or V-,

one of these diodes conducts. During normal operation

these reverse-biased ESD diodes leak, forming the only

current drawn from V- and V+.

Virtually all the analog leakage current is through the

ESD diodes. Although the ESD diodes on a given sig-

nal pin are identical, and therefore fairly well balanced,

they are reverse-biased differently. Each is biased by

either V+ or V- and the analog signal. This means their

leakages vary as the signal varies. The difference in the

two diode leakages from the signal path to the V+ and

V- pins constitutes the analog signal-path leakage cur-

rent. All analog leakage current flows to the supply ter-

minals, not to the other switch terminal. This explains

how both sides of a given switch can show leakage

currents of either the same or opposite polarity.

There is no connection between the analog signal

paths and GND. The analog signal paths consist of an

N-channel and P-channel MOSFET with their sources

and drains paralleled and their gates driven out of

phase to V+ and V- by the logic-level translators.

and GND power the internal logic and logic-level

translators, and set the input logic thresholds. The

logic-level translators convert the logic levels to

switched V+ and V- signals to drive the gates of the

analog switches. Therefore, the gate-to-source and

gate-to-drain impedances are the only connection

between the logic supplies and the analog supplies.

Bipolar-Supply Operation

The MAX4589 operates with bipolar supplies between

±2.7V and ±6V. The V+ and V- supplies are not

required to be symmetrical, but their sum cannot

exceed the absolute maximum rating of 13.0V. Do not

connect the MAX4589 V+ pin to +3V and connect the

logic-level input pins to TTL logic-level signals. This

exceeds the absolute maximum ratings, and may

cause damage to the part and/or external circuits.

CAUTION: The absolute maximum V+ to V- differen-

tial voltage is 13.0V. Typical “±6-Volt” or “12-Volt”

supplies with ±10% tolerances can be as high as

13.2V. This voltage can damage the MAX4589. Even

±5% tolerance supplies may have overshoot or

noise spikes that exceed 13.0V.

MAX4589

Low-Voltage, High-Isolation,

Dual 2-Channel RF/Video Multiplexer

______________________________________________________________________________________ 15

Single-Supply Operation

The MAX4589 operates from a single supply between

+2.7V and +12V when V- is connected to GND.

Observe all of the precautions listed in the

Bipolar-

Supply Operation

section. Note, however, that these

parts are optimized for ±5V operation, and AC and DC

characteristics are degraded significantly when operat-

ing at less than ±5V. As the overall supply voltage

(V+ to V-) is reduced, switching speed, on-resistance,

off-isolation, and distortion are degraded (see

Typical

Operating Characteristics

Single-supply operation also limits signal levels and

interferes with grounded signals. When V- = GND, AC

signals are limited to 300mV below GND. Voltages

below this level are clipped by the internal ESD-protec-

tion diodes, and the parts can be damaged if exces-

sive current flows.

Power Off

When power to the MAX4589 is off (i.e., V+ = 0 and V-

= 0), the

Absolute Maximum Ratings

still apply. This

means that none of the MAX4589 pins can exceed

±0.3V. Voltages beyond ±0.3V cause the internal ESD-

protection diodes to conduct, with potentially cata-

strophic consequences.

Power-Supply Sequencing

When applying power to the MAX4589, follow this

sequence: V+, V-, V

, then logic inputs. Apply signals

on the analog NO_ and COM_ pins any time after V+

and V- are set. Turning on all pins simultaneously is

acceptable only if the circuit design guarantees con-

current power-up.

The power-down sequence is the opposite of the

power-up sequence. That is, the V

and logic inputs

must go to zero potential before (or simultaneously

with) the V- then V+ supplies. Always observe the

Absolute Maximum Ratings

to ensure proper operation.

Grounding

DC Ground Considerations

Satisfactory high-frequency operation requires that

careful consideration be given to grounding. For most

applications, a ground plane is strongly recom-

mended and the GND pin must connect to it with

solid copper. While the V+ and V- power-supply pins

are common to all switches in a given package, each

input pair is separated with ground pins that are not

internally connected to each other. This contributes to

the overall high-frequency performance by reducing

channel-to-channel crosstalk.

The digital inputs have voltage thresholds determined by

and GND. (V- does not influence the logic-level

threshold.) With V

= +5V and GND = 0, the threshold is

about 1.6V, ensuring compatibility with TTL- and CMOS-

logic drivers.

AC Ground and Bypassing

A ground plane is mandatory for satisfactory high-

frequency operation. Prototyping using hand wiring or

wire-wrap boards is not recommended. Make the

ground plane solid metal underneath the device, with-

out interruptions. Avoid routing traces under the device

itself. For DIP packages, this applies to both sides of a

two-sided board. Failure to observe this has a minimal

effect on the “on” characteristics of the switch at high

frequencies, but it will degrade the off-isolation and

crosstalk.

When using the SO package of the MAX4589 on PC

boards with a buried ground plane, connect the GND

pins to the ground plane with a separate via. Do not

share this via with any other ground path. Providing a

ground via on both sides of the SMT land further

enhances the off-isolation by lowering the parasitic

inductance. With the DIP package, connect the

through-holes directly to the buried plane or thermally

relieve them, as required, to meet manufacturability

requirements. Again, do not use these through-hole

pads as the current path for any other components.

Bypass the V+ and V- pins to the ground plane with sur-

face-mount 0.1µF capacitors. Locate these capacitors as

close as possible to the pins on the same side of the

board as the device. Do not use feedthroughs or vias for

bypass capacitors. If board layout dictates that the

bypass capacitors are mounted on the opposite side of

the PC board, use short feedthroughs or vias, directly

under the V+ and V- pins. Use multiple vias if possible. If

V- = GND, connect it directly to the ground plane with

solid copper. Keep all traces short.

Signal Routing

Keep all signal traces as short as possible. Separate all

signal traces from each other, and keep them away

from any other traces that could induce interference.

Separating the signal traces with generously sized

ground wires also helps minimize interference. Routing

signals via coaxial cable, terminated as close to the

MAX4589 as possible, provides the highest isolation.

Board Layout

IC sockets degrade high-frequency performance and

are not recommended if signal bandwidth exceeds

5MHz. Surface-mount parts, having shorter internal

lead frames, provide the best high-frequency perfor-

mance. Keep all bypass capacitors close to the device,

and separate all signal leads with ground planes. Use

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

MAX4589EWP

Mfr. #:

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IC MUX DUAL RF VIDEO 2CH 20-SOIC

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MAX4589EWP

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