IDT6116LA45TPG

4
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
NOTES:
1. TA = + 25°C
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
DC Electrical Characteristics
(1)
(continued)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, only address inputs are toggling at fMAX, f = 0 means address inputs are not changing.
Data Retention Characteristics Over All Temperature Ranges
(LA Version Only) (VLC = 0.2V, VHC = VCC  0.2V)
Symbol
Parameter
Power
6116SA45
6116LA45
6116SA55
6116LA55
6116SA70
6116LA70
6116SA90
6116LA90
6116SA120
6116LA120
6116SA150
6116LA150
Unit
Com'l
& Ind
Mil
Mil Only
Mil Only
Mil Only
Mil Only
Mil Only
I
CC1
Operating Power Supply
Current, CS <
V
IL
,
Outputs Open
V
CC
= Max., f
=
0
SA 80 90 90 90 90 90 90
mA
LA 75 85 85 85 85 85 85
I
CC2
Dynamic Operating
Current, CS <
V
IL
,
Outputs Open
V
CC
= Max., f = f
MAX
(2 )
SA 100 100 100 100 100 100 90
mA
LA 90 95 90 90 85 85 85
I
SB
Standby Power Supply
Current (TTL Level)
CS >
V
IH
, Outputs Open
V
CC
= Max., f = f
MAX
(2 )
SA 25 25 25 25 25 25 25
mA
LA 20 20 20 20 25 15 15
I
SB1
Full Standby Power
Supply Current (CMOS
Level), CS >
V
HC
,
V
CC
= Max., V
IN
< V
LC
or V
IN
> V
HC
, f = 0
SA2101010101010
mA
LA 0.1 0.9 0.9 0.9 0.9 0.9 0.9
3089 tbl 09
Typ.
(1 )
V
CC
@
Max.
V
CC
@
Symbol
Parameter
Test Condition
Min.
2.0V
3.0V
2.0V
3.0V
Unit
V
DR
V
CC
for Data Retention
____
2.0
____
____
____
____
V
I
CCDR
Data Retention Current MIL.
COM'L.
____
____
0.5
0.5
1.5
1.5
200
20
300
30
µ
A
t
CD R
(3 )
Chip Deselect to Data
Retention Time
CS >
V
HC
V
IN
> V
HC
or < V
LC
____
0
____
____
____
ns
t
R
(3 )
Operation Recovery Time
t
RC
(2 )
____
____
____
____
ns
I
I
LI
I
Input Leakage Current
____
____
____
22
µA
3089 tbl 10
6.42
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
5
Low VCC Data Retention Waveform
AC Test Conditions
DATA RETENTION MODE
V
CC
CS
t
CDR
4.5V
V
DR
2V
V
DR
4.5V
t
R
V
IH
V
IH
3089 drw 03
,
Figure 2. AC Test Load
(for tOLZ, tCLZ, tOHZ, tWHZ, tCHZ & tOW)
Figure 1. AC Test Load
*Including scope and jig.
3089 drw 04
30pF*
255
5V
DATA
OUT
480
,
5pF*
255
5V
480
DATA
OUT
3089 drw 05
,
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
3089 tbl 11
6
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5V ± 10%, All Temperature Ranges) (continued)
NOTES:
1. 0°C to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
AC Electrical Characteristics (VCC = 5V ± 10%, All Temperature Ranges)
Symbol
Parameter
6116SA15
(1)
6116SA20
6116LA20
6116SA25
6116LA25
6116SA35
6116LA35
Unit
Min.
Max.
Min.
Max.
Min.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time 15
____
20
____
25
____
35
____
ns
t
AA
Address Access Time
____
15
____
19
____
25
____
35 ns
t
ACS
Chip Select Access Time
____
15
____
20
____
25
____
35 ns
t
CL Z
(3 )
Chip Select to Output in Low-Z 5
____
5
____
5
____
5
____
ns
t
OE
Output Enable to Output Valid
____
10
____
10
____
13
____
20 ns
t
OLZ
(3 )
Output Enable to Output in Low-Z 0
____
0
____
5
____
5
____
ns
t
CHZ
(3 )
Chip Deselect to Output in High-Z
____
10
____
11
____
12
____
15 ns
t
OHZ
(3 )
Output Disable to Output in High-Z
____
8
____
8
____
10
____
13 ns
t
OH
Output Hold from Address Change 5
____
5
____
5
____
5
____
ns
t
PU
(3 )
Chip Select to Power Up Time 0
____
0
____
0
____
0
____
ns
t
PD
(3 )
Chip Deselect to Power Down Time
____
15
____
20
____
25
____
35 ns
3089 tbl 12
Symbol
Parameter
6116SA45
6116LA45
6116SA55
(2)
6116LA55
(2)
6116SA70
(2)
6116LA70
(2)
6116SA90
(2)
6116LA90
(2)
6116SA120
(2)
6116LA120
(2)
6116SA150
(2)
6116LA150
(2)
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time 45
____
55
____
70
____
90
____
120
____
150
____
ns
t
AA
Address Access Time
____
45
____
55
____
70
____
90
____
120
____
150 ns
t
ACS
Chip Select Access Time
____
45
____
50
____
65
____
90
____
120
____
150 ns
t
CL Z
(3 )
Chip Select to Output in Low-Z 5
____
5
____
5
____
5
____
5
____
5
____
ns
t
OE
Output Enable to Output Valid
____
25
____
40
____
50
____
60
____
80
____
100 ns
t
OLZ
(3 )
Output Enable to Output in Low-Z 5
____
5
____
5
____
5
____
5
____
5
____
ns
t
CHZ
(3 )
Chip Deselect to Output in High-Z
____
20
____
30
____
35
____
40
____
40
____
40 ns
t
OHZ
(3 )
Output Disable to Output in High-Z
____
15
____
30
____
35
____
40
____
40
____
40 ns
t
OH
Output Hold from Address Change 5
____
5
____
5
____
5
____
5
____
5
____
ns
3089 tbl 13

IDT6116LA45TPG

Mfr. #:
Manufacturer:
Description:
IC SRAM 16K PARALLEL 24DIP
Lifecycle:
New from this manufacturer.
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