IDT6116LA45TPG

6.42
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
7
Timing Waveform of Read Cycle No. 2
(1,2,4)
Timing Waveform of Read Cycle No. 1
(1,3)
Timing Waveform of Read Cycle No. 3
(1,3,4)
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±500mV from steady state.
ADDRESS
OE
CS
t
RC
t
AA
t
OE
t
ACS
DATA
OUT
t
OH
t
OLZ
(5)
t
CLZ
(5)
t
OHZ
(5)
t
CHZ
(5)
3089 drw 06
DATA
VALID
t
PD
I
CC
I
SB
t
PU
V
CC
Supply
Currents
,
ADDRESS
t
RC
t
AA
t
OH
t
OH
DATA
OUT
3089 drw 07
PREVIOUS DATA VALID
DATA VALID
,
CS
t
ACS
DATA
OUT
t
CLZ
(5)
t
CHZ
(5)
DATA VALID
3089 drw 08
,
8
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5V ± 10%, All Temperature Ranges)
NOTES:
1. 0°C to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter guaranteed with AC Load (Figure 2) by device characterization, but is not production tested.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
AC Electrical Characteristics (VCC = 5V ± 10%, All Temperature Ranges) (continued)
6116SA15
(1)
6116SA20
6116LA20
6116SA25
6116LA25
6116SA35
6116LA35
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle
t
WC
Write Cycle Time 15
____
20
____
25
____
35
____
ns
t
CW
Chip Select to End-of-Write 13
____
15
____
17
____
25
____
ns
t
AW
Address Valid to End-of-Write 14
____
15
____
17
____
25
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
12
____
15
____
20
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
ns
t
WHZ
(3 )
Write to Output in High-Z
____
7
____
8
____
16
____
20 ns
t
DW
Data to Write Time Overlap 12
____
12
____
13
____
15
____
ns
t
DH
(4 )
Data Hold from Write Time 0
____
0
____
0
____
0
____
ns
t
OW
(3,4)
Output Active from End-of-Write 0
____
0
____
0
____
0
____
ns
3089 tbl 14
6116SA45
6116LA45
6116SA55
(2)
6116LA55
(2)
6116SA70
(2)
6116LA70
(2)
6116SA90
(2)
6116LA90
(2)
6116SA120
(2)
6116LA120
(2)
6116SA150
(2)
6116LA150
(2)
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle
t
WC
Write Cycle Time 45
____
55
____
70
____
90
____
120
____
150
____
ns
t
CW
Chip Select to End-of-Write 30
____
40
____
40
____
55
____
70
____
90
____
ns
t
AW
Address Valid to End-of-Write 30
____
45
____
65
____
80
____
105
____
120
____
ns
t
AS
Address Set-up Time 0
____
5
____
15
____
15
____
20
____
20
____
ns
t
WP
Write Pulse Width 25
____
40
____
40
____
55
____
70
____
90
____
ns
t
WR
Write Recovery Time 0
____
5
____
5
____
5
____
5
____
10
____
ns
t
WHZ
(3 )
Write to Output in High-Z
____
25
____
30
____
35
____
40
____
40
____
40 ns
t
DW
Data to Write Time Overlap 20
____
25
____
30
____
30
____
35
____
40
____
ns
t
DH
(4 )
Data Hold from Write Time 0
____
5
____
5
____
5
____
5
____
10
____
ns
t
OW
(3,4)
Output Active from End-of-Write 0
____
0
____
0
____
0
____
0
____
0
____
ns
3089 tbl 15
6.42
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
9
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
(1,2,5,7)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
(1,2,3,5,7)
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and the input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±500mV from steady state.
7. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers
to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse
is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.
ADDRESS
DATA
OUT
CS
WE
DATA
IN
t
WC
t
AW
3089 drw 09
t
AS
t
WHZ
(6)
(4)
t
DW
t
DH
(4)
t
OW
t
WR
t
CHZ
(6)
t
WP
(7)
(6)
PREVIOUS DATA VALID
DATA
VALID
DATA VALID
(3)
,
CS
WE
DATA
IN
t
WC
t
AW
t
CW
t
WR
(3)
t
DW
t
DH
t
AS
3089 drw 10
DATA VALID
ADDRESS
,

IDT6116LA45TPG

Mfr. #:
Manufacturer:
Description:
IC SRAM 16K PARALLEL 24DIP
Lifecycle:
New from this manufacturer.
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