Philips Semiconductors Preliminary data
P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family
8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM
2002 Jul 18
44
FLASH EPROM MEMORY
GENERAL DESCRIPTION
The P89C51RA2/RB2/RC2/RD2xx Flash memory augments EPROM
functionality with in-circuit electrical erasure and programming. The
Flash can be read and written as bytes. The Chip Erase operation will
erase the entire program memory. The Block Erase function can
erase any Flash block. In-system programming and standard parallel
programming are both available. On-chip erase and write timing
generation contribute to a user friendly programming interface.
The P89C51RA2/RB2/RC2/RD2xx Flash reliably stores memory
contents even after 10,000 erase and program cycles. The cell is
designed to optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide processing and
low internal electric fields for erase and programming operations
produces reliable cycling. The P89C51RA2/RB2/RC2/RD2xx uses a
+5 V V
PP
supply to perform the Program/Erase algorithms.
FEATURES – IN-SYSTEM PROGRAMMING (ISP)
AND IN-APPLICATION PROGRAMMING (IAP)
• Flash EPROM internal program memory with Block Erase.
• Internal 1-kbyte fixed BootROM, containing low-level in-system
programming routines and a default serial loader. User program
can call these routines to perform In-Application Programming
(IAP). The BootROM can be turned off to provide access to the
full 64-kbyte Flash memory.
• Boot Vector allows user provided Flash loader code to reside
anywhere in the Flash memory space. This configuration provides
flexibility to the user.
• Default loader in BootROM allows programming via the serial port
without the need for a user provided loader.
• Up to 64-kbyte external program memory if the internal program
memory is disabled (EA
= 0).
• Programming and erase voltage +5 V (+12 V tolerant).
• Read/Programming/Erase using ISP/IAP:
– Byte Programming (8 ms).
– Typical quick erase times:
Block Erase (4 kbyte) in 3 seconds.
Full Chip Erase:
– RD2xx (64K) in 11 seconds
– RC2 (32K) in 7 seconds
– RB2 (16K) in 5 seconds
– RA2 (4K) in 4 seconds
• Parallel programming with 87C51 compatible hardware interface
to programmer.
• In-system programming (ISP).
• In-application programming (IAP).
• Programmable security for the code in the Flash.
• 10,000 minimum erase/program cycles for each byte.
• 10-year minimum data retention.
FLASH PROGRAMMING AND ERASURE
In general, there are three methods of erasing or programming of
the Flash memory that may be used. First, the Flash may be
programmed or erased in the end-user application by calling
low-level routines through entry point in the BootROM. The end-user
application, though, must be executing code from a different block
than the block that is being erased or programmed. Second, the
on-chip ISP boot loader may be invoked. This ISP boot loader will, in
turn, call low-level routines through the common entry point in the
BootROM that can be used by end-user applications. Third, the
Flash may be programmed or erased using parallel method by using
a commercially available EPROM programmer. The parallel
programming method used by these devices is similar to that used
by EPROM 87C51, but it is not identical, and the commercially
available programmer will need to have support for these devices.
FLASH MEMORY SPACES
Flash User Code Memory Organization
The P89C51RA2/RB2/RC2/RD2xx contains 8KB/16KB/32KB/64KB
Flash user code program memory organized into 4-kbyte blocks.
ISP and IAP BootROM routines will support the new 4-kbyte block
sizes through additional block number assignments while
maintaining compatibility with previous 8-kbyte and 16-kbyte block
assignments. This memory space is programmable via IAP, ISP, and
parallel modes.
Status Byte/Boot Vector Block
This device includes a 4-kbyte block which contains the Status Byte
and Boot Vector (Status Byte Block) . The Status Byte and Boot
Vector are programmable via IAP, ISP, and parallel modes. Note that
erasing of either the Status Byte and Boot Vector will erase the
entire contents of this block. Thus the Status Byte and Boot Vector
are erased together but are programmable separately.
Security & User Configuration Block
This device includes a 4-kbyte block (Security Block) which contains
the Security Bits, the 6-clock/12-clock Flash-based clock mode bit
FX2, and 4095 user programmable bytes. This block is
programmable via IAP, ISP, and parallel modes. Security bits will
prevent, as required, parallel programmers from reading or writing,
however, IAP or ISP inhibitions will be software controlled. This
block may only be erased using full-chip erase functions in ISP, IAP,
or parallel mode. This security feature protects against software
piracy and prevents the contents of the Flash from being read. The
Security bits are located in the Flash. There are three programmable
security bits that will provide different levels of protection for the
on-chip code and data (See Table 11). The 4095 user programmable
bytes are not part of user code memory are intended to be
programmed or read through IAP, ISP, or parallel programmer
functions.
The 6-clock/12-clock Flash-based clock mode bit FX2 will be latched
at power-on. This allows the bit to be changed via IAP or ISP and
delay taking effect until the next reset. This avoids changing baud
rates during ISP operations.
Boot ROM
When the microcontroller programs its Flash memory, all of the low
level details are handled by code that is contained in a 1-kbyte
