Philips Semiconductors Preliminary data
P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family
8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM
2002 Jul 18
58
AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE)
T
amb
= 0 °C to +70 °C or –40 °C to +85 °C; V
CC
= 5 V ± 10%, V
SS
= 0 V
1,
2,
3
VARIABLE CLOCK
4
20 MHz CLOCK
4
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT
1/t
CLCL
42 Oscillator frequency 0 20 MHz
t
LHLL
42 ALE pulse width t
CLCL
–40 10 ns
t
AVLL
42 Address valid to ALE low 0.5t
CLCL
–20 5 ns
t
LLAX
42 Address hold after ALE low 0.5t
CLCL
–20 5 ns
t
LLIV
42 ALE low to valid instruction in 2t
CLCL
–65 35 ns
t
LLPL
42 ALE low to PSEN low 0.5t
CLCL
–20 5 ns
t
PLPH
42 PSEN pulse width 1.5t
CLCL
–45 30 ns
t
PLIV
42 PSEN low to valid instruction in 1.5t
CLCL
–60 15 ns
t
PXIX
42 Input instruction hold after PSEN 0 0 ns
t
PXIZ
42 Input instruction float after PSEN 0.5t
CLCL
–20 5 ns
t
AVIV
42 Address to valid instruction in 2.5t
CLCL
–80 45 ns
t
PLAZ
42 PSEN low to address float 10 10 ns
Data Memory
t
RLRH
43, 44 RD pulse width 3t
CLCL
–100 50 ns
t
WLWH
43, 44 WR pulse width 3t
CLCL
–100 50 ns
t
RLDV
43, 44 RD low to valid data in 2.5t
CLCL
–90 35 ns
t
RHDX
43, 44 Data hold after RD 0 0 ns
t
RHDZ
43, 44 Data float after RD t
CLCL
–20 5 ns
t
LLDV
43, 44 ALE low to valid data in 4t
CLCL
–150 50 ns
t
AVDV
43, 44 Address to valid data in 4.5t
CLCL
–165 60 ns
t
LLWL
43, 44 ALE low to RD or WR low 1.5t
CLCL
–50 1.5t
CLCL
+50 25 125 ns
t
AVWL
43, 44 Address valid to WR low or RD low 2t
CLCL
–75 25 ns
t
QVWX
43, 44 Data valid to WR transition 0.5t
CLCL
–25 0 ns
t
WHQX
43, 44 Data hold after WR 0.5t
CLCL
–20 5 ns
t
QVWH
44 Data valid to WR high 3.5t
CLCL
–130 45 ns
t
RLAZ
43, 44 RD low to address float 0 0 ns
t
WHLH
43, 44 RD or WR high to ALE high 0.5t
CLCL
–20 0.5t
CLCL
+20 5 45 ns
External Clock
t
CHCX
46 High time 20 t
CLCL
–t
CLCX
ns
t
CLCX
46 Low time 20 t
CLCL
–t
CHCX
ns
t
CLCH
46 Rise time 5 ns
t
CHCL
46 Fall time 5 ns
Shift Register
t
XLXL
45 Serial port clock cycle time 6t
CLCL
300 ns
t
QVXH
45 Output data setup to clock rising edge 5t
CLCL
–133 117 ns
t
XHQX
45 Output data hold after clock rising edge t
CLCL
–30 20 ns
t
XHDX
45 Input data hold after clock rising edge 0 0 ns
t
XHDV
45 Clock rising edge to input data valid 5t
CLCL
–133 117 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN
= 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.
4. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
