1
X9400
Low Noise/Low Power/SPI Bus
Quad Digitally Controlled Potentiometers
(XDCP™)
FEATURES
Four potentiometers per package
64 resistor taps
SPI serial interface for write, read, and transfer
operations of the potentiometer
Wiper resistance, 40 typical at 5V.
Four non-volatile data registers for each
potentiometer
Non-volatile storage of multiple wiper position
Power-on recall. Loads saved wiper position on
power-up.
Standby current < 1µA max
•System V
CC
: 2.7V to 5.5V operation
•Analog V
+
/V
: -5V to +5V
•10k, 2.5k end to end resistance
100 yr. data retention
Endurance: 100,000 data changes per bit per
register
Low power CMOS
24 Ld SOIC and 24 Ld TSSOP
Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9400 integrates four digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0-3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power-up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
Interface
and
Control
Circuitry
CS
SCK
SO
A0
A1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
V
H1
/R
H1
V
L1
/R
L1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
V
H0
/R
H0
V
L0
/R
L0
Data
8
V
W0
/R
W0
V
W1
/R
W1
R0 R1
R2 R3
Resistor
Array
V
H2
/R
H2
V
L2
/R
L2
V
W2
/R
W2
R0 R1
R2 R3
Resistor
Array
V
H3
/R
H3
V
L3
/R
L3
V
W3
/R
W3
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
Pot 3
Pot 2
HOLD
Pot 0
V
CC
V
SS
WP
SI
V+
V-
Data Sheet FN8189.4September 2, 2015
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005-2006, 2015. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
2
FN8189.4
September 2, 2015
Ordering Information
PART NUMBER
PART
MARKING
V
CC
LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(k)
TEMP.
RANGE
(°C) PACKAGE
PKG.
DWG. #
X9400WS24ZT1 (Note) (No longer available,
recommended replacement: X9400WS24IZT1)
X9400WS Z 5 ±10% 10 0 to +70 24 Ld SOIC (300 mil)
(Pb-free) Tape and Reel
M24.3
X9400WS24IZ* (Note) X9400WS ZI -40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9400WV24IZ* (Note) X9400WV ZI -40 to +85 24 Ld TSSOP (4.4mm)
(Pb-free)
MDP0044
X9400WV24Z* (Note) (No longer available,
recommended replacement: X9400WS24IZT1)
X9400WV Z 0 to +70 24 Ld TSSOP (4.4mm)
(Pb-free)
MDP0044
X9400WS24IZ-2.7* (Note) X9400WS ZG 2.7 to 5.5 -40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9400WV24IZ-2.7* (Note) (No longer available,
recommended replacement: X9400WS24IZT1)
X9400WV ZG -40 to +85 24 Ld TSSOP (4.4mm)
(Pb-free)
MDP0044
X9400WV24Z-2.7* (Note) (No longer available,
recommended replacement: X9400WS24IZT1)
X9400WV ZF 0 to +70 24 Ld TSSOP (4.4mm)
(Pb-free)
MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
X9400
3
FN8189.4
September 2, 2015
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9400.
Chip Select (CS
)
When CS
is HIGH, the X9400 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS
LOW enables the X9400, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS
is
required prior to the start of any operation.
Hold (HOLD
)
HOLD
is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD
may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD
must
be brought LOW while SCK is LOW. To resume
communication, HOLD
is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Device Address (A
0
- A
1
)
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9400. A maximum of 4 devices may occupy the
SPI serial bus.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
- V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
-
V
L3
/R
L3
)
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
V
W
/R
W
(V
W0
/R
W0
- V
W3
/R
W3
)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP
)
The WP
pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog Supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
V
CC
V
L0
/R
L0
V
H0
/R
H0
WP
SI
A
1
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
V+
V
L3
/R
L3
V
H3
/R
H3
V
W3
/R
W3
A
0
SO
HOLD
SCK
V
L2
/R
L2
V
H2
/R
H2
SOIC
X9400
V
SS
V
W0
/R
W0
14
13
11
12
CS
V
L1
/R
L1
V
H1
/R
H1
V
W1
/R
W1
V
W2
/R
W2
V-
SI
A
1
V
H2
/R
H2
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
WP
CS
V
W0
/R
W0
V
CC
V+
V
L3
/R
L3
V
H3
/R
H3
V
W3
/R
W3
TSSOP
X9400
V
W2
/R
W2
14
13
11
12
HOLD
V
L1
/R
L1
V
H1
/R
H1
V
W1
/R
W1
A
0
SO
V
H0
/R
H0
V-
SCK
V
L2
/R
L2
V
L0
/R
L0
V
SS
X9400

X9400WS24IZT1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs X9400WS24IZ QD CMOS EEPOT 10KOHM S IND
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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