13
FN8189.4
September 2, 2015
A.C. TEST CONDITIONS
Notes: (4) This parameter is periodically sampled and not 100% tested
(5) t
PUR
and t
PUW
are the delays required from the time the
third (last) power supply (V
CC
, V+ or V-) is stable until the
specific instruction can be issued. These parameters are
periodically sampled and not 100% tested.
SPICE Macro Model
SYMBOL TABLE
AC TIMING
I
nput pulse levels V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times 10ns
Input and output timing level V
CC
x 0.5
10pF
R
H
R
TOTAL
C
H
25pF
C
W
C
L
10pF
R
W
R
L
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
Symbol Parameter Min. Max. Unit
f
SCK
SSI/SPI clock frequency 2.0 MHz
t
CYC
SSI/SPI clock cycle time 500 ns
t
WH
SSI/SPI clock high time 200 ns
t
WL
SSI/SPI clock low time 200 ns
t
LEAD
Lead time 250 ns
t
LAG
Lag time 250 ns
t
SU
SI, SCK, HOLD and CS input setup time 50 ns
t
H
SI, SCK, HOLD and CS input hold time 50 ns
t
RI
SI, SCK, HOLD and CS input rise time 2 µs
t
FI
SI, SCK, HOLD and CS input fall time 2 µs
t
DIS
SO output disable time 0 500 ns
t
V
SO output valid time 100 ns
t
HO
SO output hold time 0 ns
t
RO
SO output rise time 50 ns
t
FO
SO output fall time 50 ns
t
HOLD
HOLD time 400 ns
t
HSU
HOLD setup time 100 ns
t
HH
HOLD hold time 100 ns
t
HZ
HOLD low to output in High Z 100 ns
t
LZ
HOLD high to output in Low Z 100 ns
T
I
Noise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns
t
CS
CS deselect time 2 µs
t
WPASU
WP, A0 and A1 setup time 0 ns
t
WPAH
WP, A0 and A1 hold time 0 ns
X9400
