709089L15PFI8 Datasheet 709079L15PF, 709079S12PF, 709089L9PF8 | P1-P3

FEBRUARY 2016

DSC-3242/16

1

Functional Block Diagram

Features:

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

◆

High-speed clock to data access

– Commercial: 9/12/15ns (max.)

– Industrial: 12ns (max.)

◆

Low-power operation

– IDT709089/79S

Active: 950mW (typ.)

Standby: 5mW (typ.)

– IDT709089/79L

Active: 950mW (typ.)

Standby: 1mW (typ.)

◆

Flow-Through or Pipelined output mode on either port via

the FT/PIPE pin

◆

Counter enable and reset features

◆

Dual chip enables allow for depth expansion without

additional logic

◆

Full synchronous operation on both ports

– 4ns setup to clock and 1ns hold on all control, data,

and address inputs

– Data input, address, and control registers

– Fast 9ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– 15ns cycle time, 66.7MHz operation in the Pipelined

output mode

◆

TTL- compatible, single 5V (±10%) power supply

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

Available in 100-pin Thin Quad Flatpack (TQFP) package

◆

Green parts available, see ordering information

HIGH-SPEED 64/32K x 8

SYNCHRONOUS

DUAL-PORT STATIC RAM

IDT709089/79S/L

0

1

0/1

1

0/1

0

R/W

R

OE

R

CE

0R

CE

1R

FT/PIPE

R

I/O

Control

MEMORY

ARRAY

Counter/

Address

Reg.

I/O

Control

3242 drw 01

A

15R

(1)

A

0R

CLK

R

ADS

R

CNTEN

R

CNTRST

R

A

0L

CLK

L

ADS

L

A

15L

(1)

CNTEN

L

CNTRST

L

Counter/

Address

Reg.

R/W

L

CE

0L

OE

L

CE

1L

I/O

0L

-I/O

7L

I/O

0R

-I/O

7R

.

1

0/1

0

1

0/1

FT/PIPE

L

NOTE:

1. A15X is a NC for IDT709079.

6.42

IDT709089/79S/L

High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

2

Description:

The IDT709089/79 is a high-speed 64/32K x 8 bit synchronous Dual-

Port RAM. The memory array utilizes Dual-Port memory cells to allow

simultaneous access of any address from both ports. Registers on control,

data, and address inputs provide minimal setup and hold times. The timing

latitude provided by this approach allows systems to be designed with very

short cycle times.

Pin Configuration

(1,2,3)

NOTES:

1. A15X is a NC for IDT709079.

2. All VCC pins must be connected to power supply.

3. All GND pins must be connected to ground supply.

4. Package body is approximately 14mm x 14mm x 1.4mm.

5. This package code is used to reference the package diagram.

With an input data register, the IDT709089/79 has been optimized for

applications having unidirectional or bidirectional data flow in bursts.

An automatic power down feature, controlled by CE0 and CE1, permits

the on-chip circuitry of each port to enter a very low standby power

mode. Fabricated using CMOS high-performance technology, these

devices typically operate on only 950mW of power.

Index

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

709089/79

(5)

PN100

NC

GND

FT/PIPE

R

OER

R/WR

CNTRST

R

CE1R

CE0R

NC

GND

A

15R

A

12R

A

13R

A

11R

A

10R

A

9R

A

8R

A

7R

NC

A

14R

NC

3242 drw 02

NC

FT/PIPE

L

OEL

R/W

L

CNTRST

L

CE1L

CE0L

NC

V

CC

NC

A15L

A

14L

A13L

A8L

A7L

NC

A

12L

A11L

A10L

A9L

NC

I/O

6R

I/O5R

I/O4R

I/O3R

V

CC

I/O2R

I/O

0R

GND

V

CC

I/O0L

I/O1L

GND

I/O

2L

I/O4L

I/O5L

I/O6L

I/O

3L

I/O1R

I/O7R

GND

NC

A

6R

A

5R

A4R

A3R

A2R

A1R

A0R

CNTEN

R

CLKR

ADS

R

ADSL

CLKL

CNTEN

L

A

0L

GND

A

2L

A3L

A5L

A

6L

NC

A

1L

A4L

I/O

7L

6.42

IDT709089/79S/L

High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

3

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. CE0 and OE = VIL; CE1 and R/W = VIH.

3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.

4. ADS is independent of all other signals including CE0 and CE1.

5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.

Truth Table II—Address Counter Control

(1,2)

Truth Table I—

Read/Write and Enable Control

(1,2,3)

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = X.

3. OE is an asynchronous input signal.

OE

CLK

CE

0

CE

1

R/W I/O

0-7

Mode

X

↑

H X X High-Z Deselected

X

↑

X L X High-Z Deselected

X

↑

LHL D

IN

Write

L

↑

LHHD

OUT

Read

H X L H X High-Z Outputs Disabled

3242 tbl 02

External

Address

Internal

Address

Used CLK

ADS CNTEN CNTRST

I/O

(3)

MODE

An X An

↑

L

(4)

XHD

I/O

(n) External Address Used

XAnAn + 1

↑

H L

(5)

HD

I/O

(n+1) Counter Enabled—Internal Address generation

X An + 1 An + 1

↑

HH HD

I/O

(n+1) External Address Blocked—Counter disabled (An + 1 reused)

XXA

0

↑

XX L

(4)

D

I/O

(0) Counter Reset to Address 0

5640 tbl 03

Pin Names

Left Port Right Port Names

CE

0L

,

CE

1L

CE

0R

,

CE

1R

Chip Enables

R/W

L

R/W

R

Read/Write Enable

OE

L

OE

R

Output Enable

A

0L

- A

15L

(1)

A

0R

- A

15R

(1)

Address

I/O

0L

- I/O

7L

I/O

0R

- I/O

7R

Data Input/Output

CLK

L

CLK

R

Clock

ADS

L

ADS

R

Address Strobe

CNTEN

L

CNTEN

R

Counter Enable

CNTRST

L

CNTRST

R

Counter Reset

FT/PIPE

L

FT/PIPE

R

Flow-Through/Pipeline

V

CC

Power

GND Ground

3242 tbl 01

NOTE:

1. A15X is a NC for IDT709079.

709089L15PFI8

709089L15PFI8

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