6.42
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
7
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device
characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a DC
signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)
(3,4)
(VCC = 5V ± 10%)
709089/79X9
Com'l Only
709089/79X12
Com'l
& Ind
709089/79X15
Com'l Only
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
t
CYC1
Clock Cycle Time (Flow-Through)
(2)
25
____
30
____
35
____
ns
t
CYC2
Clock Cycle Time (Pipelined)
(2)
15
____
20
____
25
____
ns
t
CH1
Clock High Time (Flow-Through)
(2)
12
____
12
____
12
____
ns
t
CL1
Clock Low Time (Flow-Through)
(2)
12
____
12
____
12
____
ns
t
CH2
Clock High Time (Pipelined)
(2)
6
____
8
____
10
____
ns
t
CL2
Clock Low Time (Pipelined)
(2)
6
____
8
____
10
____
ns
t
R
Clock Rise Time
____
3
____
3
____
3ns
t
F
Clock Fall Time
____
3
____
3
____
3ns
t
SA
Address Setup Time 4
____
4
____
4
____
ns
t
HA
Address Hold Time 1
____
1
____
1
____
ns
t
SC
Chip Enable Setup Time 4
____
4
____
4
____
ns
t
HC
Chip Enable Hold Time 1
____
1
____
1
____
ns
t
SW
R/W Setup Time 4
____
4
____
4
____
ns
t
HW
R/W Hold Time 1
____
1
____
1
____
ns
t
SD
Input Data Setup Time 4
____
4
____
4
____
ns
t
HD
Input Data Hold Time 1
____
1
____
1
____
ns
t
SAD
ADS Setup Time
4
____
4
____
4
____
ns
t
HAD
ADS Hold Time
1
____
1
____
1
____
ns
t
SCN
CNTEN Setup Time
4
____
4
____
4
____
ns
t
HCN
CNTEN Hold Time
1
____
1
____
1
____
ns
t
SRST
CNTRST Setup Time
4
____
4
____
4
____
ns
t
HRST
CNTRST Hold Time
1
____
1
____
1
____
ns
t
OE
Output Enable to Data Valid
____
9
____
12
____
15 ns
t
OLZ
Output Enable to Output Low-Z
(1)
2
____
2
____
2
____
ns
t
OHZ
Output Enable to Output High-Z
(1)
17 17 17ns
t
CD1
Clock to Data Valid (Flow-Through)
(2)
____
20
____
25
____
30 ns
t
CD2
Clock to Data Valid (Pipelined)
(2)
____
9
____
12
____
15 ns
t
DC
Data Output Hold After Clock High 2
____
2
____
2
____
ns
t
CKHZ
Clock High to Output High-Z
(1)
292929ns
t
CKLZ
Clock High to Output Low-Z
(1)
2
____
2
____
2
____
ns
Port-to-Port Delay
t
CWDD
Write Port Clock High to Read Data Delay
____
35
____
40
____
50 ns
t
CCS
Clock-to-Clock Setup Time
____
15
____
15
____
20 ns
3242 tbl 11
