2001-2012 Microchip Technology Inc. DS21425C-page 3
TC4467/TC4468/TC4469
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
Supply Voltage...............................................................+20 V
Input Voltage.............................(GND – 5 V) to (V
DD
+ 0.3 V)
Package Power Dissipation: (T
A
70°C)
PDIP...................................................................800 mW
CERDIP .............................................................840 mW
SOIC ..................................................................760 mW
Package Thermal Resistance:
CERDIP R
J-A
...................................................100°C/W
CERDIP R
J-C
.....................................................23°C/W
PDIP R
J-A
..........................................................80°C/W
PDIP R
J-C
..........................................................35°C/W
SOIC R
J-A
..........................................................95°C/W
SOIC R
J-C
..........................................................28°C/W
Operating Temperature Range:
C Version ...................................................0°C to +70°C
E Version.................................................-40°C to +85°C
M Version..............................................-55°C to +125°C
Maximum Chip Temperature.......................................+150°C
Storage Temperature Range.........................-65°C to +150°C
†Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, T
A
= +25°C, with 4.5 V V
DD
18 V.
Parameters Sym Min Typ Max Units Conditions
Input
Logic 1, High Input Voltage V
IH
2.4 — V
DD
V Note 3
Logic 0, Low Input Voltage V
IL
——0.8VNote 3
Input Current I
IN
-1.0 — +1.0 µA 0 VV
IN
V
DD
Output
High Output Voltage V
OH
V
DD
– 0.025 — — V I
LOAD
= 100 µA (Note 1)
Low Output Voltage V
OL
——0.15VI
LOAD
= 10 mA (Note 1)
Output Resistance R
O
—1015 I
OUT
= 10 mA, V
DD
= 18 V
Peak Output Current I
PK
—1.2—A
Continuous Output Current I
DC
— — 300 mA Single Output
— — 500 Total Package
Latch-Up Protection Withstand
Reverse Current
I — 500 — mA 4.5 VV
DD
16 V
Switching Time (Note 1)
Rise Time t
R
— 15 25 nsec Figure 4-1
Fall Time t
F
— 15 25 nsec Figure 4-1
Delay Time t
D1
— 40 75 nsec Figure 4-1
Delay Time t
D2
— 40 75 nsec Figure 4-1
Power Supply
Power Supply Current I
S
—1.54mA
Power Supply Voltage V
DD
4.5 — 18 V Note 2
Note 1: Totem pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to
drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device. Switching
times are ensured by design.
2: When driving all four outputs simultaneously in the same direction, V
DD
will be limited to 16 V. This reduces the chance that internal dv/dt
will cause high-power dissipation in the device.
3: The input threshold has approximately 50 mV of hysteresis centered at approximately 1.5 V. Input rise times should be kept below 5 µsec
to avoid high internal peak currents during input transitions. Static input levels should also be maintained above the maximum, or below
the minimum, input levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.
