CY29351AXIT Datasheet CY29351AXIT, CY29351AXI | P1-P3

CY29351

2.5V or 3.3V, 200 MHz,

9-Output Zero Delay Buffer

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-07475 Rev. *D Revised March 08, 2011

Features

■ Output Frequency Range: 25 MHz to 200 MHz

■ Input Frequency Range: 25 MHz to 200 MHz

■ 2.5V or 3.3V Operation

■ Split 2.5V and 3.3V Outputs

■ ±2.5% Max Output Duty Cycle Variation

■ Nine Clock Outputs: Drive up to 18 Clock Lines

■ Two Reference Clock Inputs: LVPECL or LVCMOS

■ 150-ps Max Output-Output Skew

■ Phase-locked Loop (PLL) Bypass Mode

■ Spread Aware

■ Output Enable or Disable

■ Pin-compatible with MPC9351

■ Industrial Temperature Range: –40°C to +85°C

■ 32-pin 1.0-mm TQFP Package

Functional Description

The CY29351 is a low voltage high performance 200 MHz

PLL-based zero delay buffer designed for high speed clock distri-

bution applications.

The CY29351 features LVPECL and LVCMOS reference clock

inputs and provides nine outputs partitioned in four banks of one,

one, two, and five outputs. Bank A divides the VCO output by two

or four while the other banks divide by four or eight per SEL(A:D)

settings (Table 3, “Function Table,” on page 3). These dividers

enable output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each

LVCMOS compatible output can drive 50 series or parallel

terminated transmission lines. For series terminated trans-

mission lines, each output can drive one or two traces giving the

device an effective fanout of 1:18.

The PLL is ensured stable given that the VCO is configured to

run between 200 MHz to 500 MHz. This allows a wide range of

output frequencies from 25 MHz to 200 MHz. For normal

operation, the external feedback input, FB_IN, is connected to

one of the outputs. The internal VCO is running at multiples of

the input reference clock set by the feedback divider (Table 2,

“Frequency Table,” on page 3).

When PLL_EN# is LOW, PLL is bypassed and the reference

clock directly feeds the output dividers. This mode is fully static

and the minimum input clock frequency specification does not

apply.

Phase

Detector

LPF





QC0

QC1

QD0

QD1

QD2

QD3

QD4

SELA

PLL_EN

TCLK

REF_SEL

PECL_CLK

FB_IN

SELB

SELC

OE#

SELD

VCO

200 -

500 MHz

Logic Block Diagram

[+] Feedback

CY29351

Document Number: 38-07475 Rev. *D Page 2 of 10

Pinout

Figure 1. Pin Diagram - 32-Pin TQFP Package

Table 1. Pin Definitions - 32-Pin TQFP Package

CY29351

REF_SEL

PLL_EN

TCLK

VSS

VDDQB

VSS

PECL_CLK#

OE#

VDD

QD4

VSS

QD3

VDDQD

QD2

QC0

VDDQC

QC1

VSS

QD0

VDDQD

QD1

VSS

AVDD

FB_IN

SELA

SELB

SELC

SELD

AVSS

PECL_CLK

[1]

Name I/O Type Description

8 PECL_CLK I, PU LVPECL LVPECL reference clock input

9 PECL_CLK# I, PU/PD LVPECL LVPECL reference clock input. Weak pull up to VDD/2.

30 TCLK I, PD LVCMOS LVCMOS/LVTTL reference clock input

28 QA O LVCMOS Clock output bank A

26 QB O LVCMOS Clock output bank B

22, 24 QC(1,0) O LVCMOS Clock output bank C

12, 14, 16, 18, 20 QD(4:0) O LVCMOS Clock output bank D

2 FB_IN I, PD LVCMOS Feedback clock input. Connect to an output for normal operation. This

input should be at the same voltage rail as input reference clock

10 OE# I, PD LVCMOS Output enable/disable input

31 PLL_EN I, PU LVCMOS PLL enable/disable input

32 REF_SEL I, PD LVCMOS Reference select input

3, 4, 5, 6 SEL(A:D) I, PD LVCMOS Frequency select input, bank (A:D)

27 VDDQB Supply VDD 2.5V or 3.3V power supply for bank B output clock

[2,3]

23 VDDQC Supply VDD 2.5V or 3.3V power supply for bank C output clocks

[2,3]

15, 19 VDDQD Supply VDD 2.5V or 3.3V power supply for bank D output clocks

[2,3]

1 AVDD Supply VDD 2.5V or 3.3V power supply for PLL

[4,5]

11 VDD Supply VDD 2.5V or 3.3V power supply for core, inputs, and bank A output clock

[2,3]

7 AVSS Supply Ground Analog ground

13, 17, 21, 25, 29 VSS Supply Ground Common ground

Notes

1. PU = Internal pull up, PD = Internal pull down.

2. A 0.1-F bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, the

high-frequency filtering characteristics are cancelled by the lead inductance of the traces.

3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD power supply pins.

4. Driving one 50 parallel terminated transmission line to a termination voltage of V

. Alternatively, each output drives up to two 50  series terminated

transmission lines.

5. Inputs have pull up or pull down resistors that affect the input current.

[+] Feedback

CY29351

Document Number: 38-07475 Rev. *D Page 3 of 10

Table 2. Frequency Table

Table 3. Function Table

Absolute Maximum Conditions

Feedback Output Divider VCO

Input Frequency Range

(AVDD = 3.3V)

Input Frequency Range

(AVDD = 2.5V)

2 Input Clock * 2 100 MHz to 200 MHz 100 MHz to 190 MHz

4 Input Clock * 4 50 MHz to 125 MHz 50 MHz to 95 MHz

8 Input Clock * 8 25 MHz to 62.5 MHz 25 MHz to 47.5 MHz

Control Default 0 1

REF_SEL 0 PCLK TCLK

PLL_EN 1 Bypass mode, PLL disabled. The input clock

connects to the output dividers

PLL enabled. The VCO output connects to the output

dividers

OE# 0 Outputs enabled Outputs disabled (three-state), VCO running at its

minimum frequency

SELA 0  2 (bank A)  4 (bank A)

SELB 0  4 (bank B)  8 (bank B)

SELC 0  4 (bank C)  8 (bank C)

SELD 0  4 (bank D)  8 (bank D)

Parameter Description Condition Min Max Unit

DC supply voltage –0.3 5.5 V

DC operating voltage Functional 2.375 3.465 V

DC input voltage Relative to V

–0.3 V

+ 0.3 V

OUT

DC output voltage Relative to V

–0.3 V

+ 0.3 V

Output termination voltage – V

 2V

LU Latch-up immunity Functional 200 – mA

Power supply ripple Ripple frequency < 100 kHz – 150 mVp-p

Temperature, storage Non Functional –65 +150



Temperature, operating ambient Functional –40 +85



Temperature, junction Functional – +150



Dissipation, junction to case Functional 42



C/W

Dissipation, junction to ambient Functional 105



C/W

ESD

ESD protection (human body model) 2000 – Volts

FIT Failure in time Manufacturing test 10 ppm

[+] Feedback

P1-P3 P4-P6 P7-P9 P10-P10

CY29351AXIT

Mfr. #:

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Manufacturer:

Cypress Semiconductor

Description:

Phase Locked Loops - PLL 2.5/3.3V 200MHz IND

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CY29351AXIT

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