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CY29351AXIT

P1-P3P4-P6P7-P9P10-P10
CY29351
Document Number: 38-07475 Rev. *D Page 4 of 10
DC Electrical Specifications
(V
DD
= 2.5V ± 5%, T
A
= –40 C to +85 C)
DC Electrical Specifications
(V
DD
= 3.3V ± 5%, T
A
= –40 C to +85 C)
Parameter Description Condition Min Typ Max Unit
V
IL
Input voltage, low LVCMOS – – 0.7 V
V
IH
Input voltage, high LVCMOS 1.7 – V
DD
+0.3 V
V
PP
Peak-Peak input voltage LVPECL 250 – 1000 mV
V
CMR
Common mode range
[6]
LVPECL 1.0 – V
DD
– 0.6 V
V
OL
Output voltage, low
[4]
I
OL
= 15mA – – 0.6 V
V
OH
Output voltage, high
[4]
I
OH
= –15mA 1.8 – – V
I
IL
Input current, low
[5]
V
IL
= V
SS
– – –100 A
I
IH
Input current, high
[5]
V
IL
= V
DD
––100A
I
DDA
PLL supply current AVDD only – 5 10 mA
I
DDQ
Quiescent supply current All V
DD
pins except AVDD – – 7 mA
I
DD
Dynamic supply current Outputs loaded at 100 MHz – 180 – mA
Outputs loaded at 200 MHz – 210 –
C
IN
Input pin capacitance – 4 – pF
Z
OUT
Output impedance 14 18 22
Parameter Description Condition Min Typ Max Unit
V
IL
Input voltage, low LVCMOS – – 0.8 V
V
IH
Input voltage, high LVCMOS 2.0 – V
DD
+ 0.3 V
V
PP
Peak-Peak input voltage LVPECL 250 – 1000 mV
V
CMR
Common mode range
[6]
LVPECL 1.0 – V
DD
– 0.6 V
V
OL
Output Voltage, Low
[4]
I
OL
= 24 mA – – 0.55 V
I
OL
= 12 mA – – 0.30
V
OH
Output voltage, high
[4]
I
OH
= –24 mA 2.4 – – V
I
IL
Input current, low
[5]
V
IL
= V
SS
– – –100 A
I
IH
Input current, high
[5]
V
IL
= V
DD
––100A
I
DDA
PLL supply current AVDD only – 5 10 mA
I
DDQ
Quiescent supply current All VDD pins except AVDD – – 7 mA
I
DD
Dynamic supply current Outputs loaded at 100 MHz – 270 – mA
Outputs loaded at 200 MHz – 300 –
C
IN
Input pin capacitance – 4 – pF
Z
OUT
Output impedance 12 15 18
[+] Feedback
CY29351
Document Number: 38-07475 Rev. *D Page 5 of 10
AC Electrical Specifications
(V
DD
= 2.5V ± 5%, T
A
= –40C to +85C)
[7]
Parameter Description Condition Min Typ Max Unit
f
VCO
VCO frequency 200 – 380 MHz
f
in
Input frequency 2 feedback 100 – 190 MHz
4 feedback 50 – 95
8 feedback 25 – 47.5
Bypass mode (PLL_EN = 0) 0 – 200
f
refDC
Input duty cycle 25 – 75 %
V
PP
Peak-Peak input voltage LVPECL 500 – 1000 mV
V
CMR
Common mode range
[8]
LVPECL 1.2 – V
DD
– 0.6 V
t
r
, t
f
TCLK input rise/fall time 0.7V to 1.7V – – 1.0 ns
f
MAX
Maximum output frequency 2 output 100 – 190 MHz
4 output 50 – 95
8 output 25 – 47.5
DC Output duty cycle f
MAX
< 100 MHz 47.5 – 52.5 %
f
MAX
> 100 MHz 45 – 55
t
r
, t
f
Output rise/fall times 0.6V to 1.8V 0.1 – 1.0 ns
t
()
Propagation delay (static phase offset) TCLK to FB_IN –100 – 100 ps
PCLK to FB_IN –100 – 100
t
sk(O)
Output-to-Output skew – – 150 ps
t
PLZ, HZ
Output disable time – – 10 ns
t
PZL, ZH
Output enable time – – 10 ns
BW PLL closed loop bandwidth (–3dB) 2 feedback – 2.2 – MHz
4 feedback – 0.85 –
8 feedback – 0.6 –
t
JIT(CC)
Cycle-to-Cycle jitter Same frequency – – 150 ps
Multiple frequencies – – 250
t
JIT(PER)
Period jitter Same frequency – – 100 ps
Multiple frequencies – – 175
t
JIT()
I/O phase jitter – 175 – ps
t
LOCK
Maximum PLL lock time – – 1 ms
Notes
7. AC characteristics apply for parallel output termination of 50 to V
TT
. Parameters are guaranteed by characterization and are not 100% tested.
8. V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range and the input swing lies
within the V
PP
(AC) specification. Violation of V
CMR
or V
PP
impacts static phase offset t().
[+] Feedback
CY29351
Document Number: 38-07475 Rev. *D Page 6 of 10
AC Electrical Specifications
(V
DD
= 3.3V ± 5%, T
A
= –40C to +85C)
[7]
Parameter Description Condition Min Typ. Max Unit
f
VCO
VCO frequency 200 – 500 MHz
f
in
Input frequency 2 feedback 100 – 200 MHz
4 feedback 50 – 125
8 feedback 25 – 62.5
Bypass mode (PLL_EN = 0) 0 – 200
f
refDC
Input duty cycle 25 – 75 %
V
PP
Peak-Peak input voltage LVPECL 500 – 1000 mV
V
CMR
Common mode range
[8]
LVPECL 1.2 – V
DD
– 0.9 V
t
r
, t
f
TCLK input rise/fall time 0.8V to 2.0V – – 1.0 ns
f
MAX
Maximum output frequency 2 output 100 – 200 MHz
4 output 50 – 125
8 output 25 – 62.5
DC Output duty cycle f
MAX
< 100 MHz 47.5 – 52.5 %
f
MAX
> 100 MHz 45 – 55
t
r
, t
f
Output rise/fall times 0.8V to 2.4V 0.1 – 1.0 ns
t
()
Propagation delay (static phase
offset)
TCLK to FB_IN, same VDD –100 – 100 ps
PCLK to FB_IN, same VDD –100 – 100
t
sk(O)
Output-to-Output skew Banks at same voltage – – 150 ps
tsk(B) Bank-to-Bank skew Banks at different voltages – – 350 ps
t
PLZ, HZ
Output disable time – – 10 ns
t
PZL, ZH
Output enable time – – 10 ns
BW PLL closed loop bandwidth (–3dB) 2 feedback – 2.2 – MHz
4 feedback – 0.85 –
8 feedback – 0.6 –
t
JIT(CC)
Cycle-to-Cycle jitter Same frequency – – 150 ps
Multiple frequencies – – 250
t
JIT(PER)
Period jitter Same frequency – – 100 ps
Multiple frequencies – – 150
t
JIT()
I/O phase jitter I/O same V
DD
– 175 – ps
t
LOCK
Maximum PLL lock time – – 1 ms
[+] Feedback
P1-P3P4-P6P7-P9P10-P10

CY29351AXIT

Mfr. #:
Buy CY29351AXIT
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 2.5/3.3V 200MHz IND
Lifecycle:
New from this manufacturer.
Delivery:
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