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MT8870DS1-1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
MT8870D/MT8870D-1 Data Sheet
4
Zarlink Semiconductor Inc.
Decoder Section
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the
incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm
protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency
deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the
detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry
specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition
will cause ESt to assume an inactive state (see “Steering Circuit”).
Figure 4 - Basic Steering Circuit
Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
causes v
c
(see Figure 4) to rise as the capacitor discharges. Provided signal condition is maintained (ESt remains
high) for the validation period (t
GTP
), v
c
reaches the threshold (V
TSt
) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and
drives v
c
to V
DD
. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the
output latch to settle, the delayed steering output flag (StD) goes high, signalling that a received tone pair has been
registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state
control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between
signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal
interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting
the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system
requirements.
Guard Time Adjustment
In many situations not requiring selection of tone duration and interdigital pause, the simple steering circuit shown
in Figure 4 is applicable. Component values are chosen according to the formula:
t
REC
=t
DP
+t
GTP
t
ID
=t
DA
+t
GTA
V
DD
C
v
c
V
DD
St/GT
ESt
StD
MT8870D/
MT8870D-1
R
t
GTA
=(RC)In(V
DD
/V
TSt
)
t
GTP
=(RC)In[V
DD
/(V
DD
-V
TSt
)]
MT8870D/MT8870D-1 Data Sheet
5
Zarlink Semiconductor Inc.
The value of t
DP
is a device parameter (see Figure 11) and t
REC
is the minimum signal duration to be recognized by
the receiver. A value for C of 0.1 µF is recommended for most applications, leaving R to be selected by the
designer.
Figure 5 - Guard Time Adjustment
Table 1 - Functional Decode Table
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE
X = DON‘T CARE
Digit TOE INH ESt Q
4
Q
3
Q
2
Q
1
ANYLXHZZZZ
1HXH0001
2HXH0010
3HXH0011
4HXH0100
5HXH0101
6HXH0110
7HXH0111
8HXH1000
9HXH1001
0HXH1010
*HXH1011
#HXH1100
AHLH1101
BHLH1110
CHLH1111
DHLH0000
AHHL
undetected, the output code
will remain the same as the
previous detected code
BHHL
CHHL
DHHL
V
DD
St/GT
ESt
C
1
R
1
R
2
a) decreasing t
GTP
; (t
GTP
<t
GTA
)
t
GTP
=(R
P
C
1
)In[V
DD
/(V
DD
-V
TSt
)]
t
GTA
=(R
1
C
1
)In(V
DD
/V
TSt
)
R
P
=(R
1
R
2
)/(R
1
+R
2
)
V
DD
St/GT
ESt
C
1
R
1
R
2
t
GTP
=(R
1
C
1
)In[V
DD
/(V
DD
-V
TSt
)]
t
GTA
=(R
P
C
1
)In(V
DD
/V
TSt
)
R
P
=(R
1
R
2
)/(R
1
+R
2
)
b) decreasing t
GTA
; (t
GTP
>t
GTA
)
MT8870D/MT8870D-1 Data Sheet
6
Zarlink Semiconductor Inc.
Different steering arrangements may be used to select independently the guard times for tone present (t
GTP
) and
tone absent (t
GTA
). This may be necessary to meet system specifications which place both accept and reject limits
on both tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system
parameters such as talk off and noise immunity. Increasing t
REC
improves talk-off performance since it reduces the
probability that tones simulated by speech will maintain signal condition long enough to be registered. Alternatively,
a relatively short t
REC
with a long t
DO
would be appropriate for extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure
5.
Power-down and Inhibit Mode
A logic high applied to pin 6 (PWDN) will power down the device to minimize the power consumption in a standby
mode. It stops the oscillator and the functions of the filters.
Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of tones representing
characters A, B, C, and D. The output code will remain the same as the previous detected code (see Table 1).
Differential Input Configuration
The input arrangement of the MT8870D/MT8870D-1 provides a differential-input operational amplifier as well as a
bias source (V
Ref
) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback
resistor to the op-amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are
connected as shown in Figure 10 with the op-amp connected for unity gain and V
Ref
biasing the input at
1
/
2
V
DD
.
Figure 6 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R
5
.
Crystal Oscillator
The internal clock circuit is completed with the addition of an external 3.579545 MHz crystal and is normally
connected as shown in Figure 10 (Single-Ended Input Configuration). However, it is possible to configure several
MT8870D/MT8870D-1 devices employing only a single oscillator crystal. The oscillator output of the first device in
the chain is coupled through a 30 pF capacitor to the oscillator input (OSC1) of the next device. Subsequent
devices are connected in a similar fashion. Refer to Figure 7 for details. The problems associated with unbalanced
loading are not a concern with the arrangement shown, i.e., precision balancing capacitors are not required.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

MT8870DS1-1

Mfr. #:
Buy MT8870DS1-1
Manufacturer:
Microchip / Microsemi
Description:
Telecom Interface ICs Pb Free DTMF RECEIVER PREMIUM SOIC
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