Operation modes M48Z02, M48Z12
10/22 Doc ID 2420 Rev 9
Table 4. WRITE mode AC characteristics
2.3 Data retention mode
With valid V
CC
applied, the M48Z02/12 operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
CC
falls within the V
PFD
(max), V
PFD
(min) window. All outputs
become high impedance, and all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
PFD
(min), the
user can be assured the memory will be in a write protected state, provided the V
CC
fall time
is not less than t
F
. The M48Z02/12 may respond to transient noise spikes on V
CC
that reach
into the deselect window during the time the device is sampling V
CC
. Therefore, decoupling
of the power supply lines is recommended.
The power switching circuit connects external V
CC
to the RAM and disconnects the battery
when V
CC
rises above V
SO
. As V
CC
rises, the battery voltage is checked. If the voltage is
too low, an internal Battery Not OK (BOK
) flag will be set. The BOK flag can be checked
after power up. If the BOK
flag is set, the first WRITE attempted will be blocked. The flag is
automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 7
on page 11 illustrates how a BOK
check routine could be structured.
For more information on a battery storage life refer to the application note AN1012.
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= 0 to 70 °C or –40 to 85 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
M48Z02/M48Z12
Unit–70 –150 –200
Min Max Min Max Min Max
t
AVAV
WRITE cycle time 70 150 200 ns
t
AVWL
Address valid to WRITE enable low 0 0 0 ns
t
AVEL
Address valid to chip enable 1 low 0 0 0 ns
t
WLWH
WRITE enable pulse width 50 90 120 ns
t
ELEH
Chip enable low to chip enable 1 high 55 90 120 ns
t
WHAX
WRITE enable high to address transition 0 10 10 ns
t
EHAX
Chip enable high to address transition 0 10 10 ns
t
DVWH
Input valid to WRITE enable high 30 40 60 ns
t
DVEH
Input valid to chip enable high 30 40 60 ns
t
WHDX
WRITE enable high to input transition 5 5 5 ns
t
EHDX
Chip enable high to input transition 5 5 5 ns
t
WLQZ
WRITE enable low to output Hi-Z 25 50 60 ns
t
AVWH
Address valid to WRITE enable high 60 120 140 ns
t
AVEH
Address valid to chip enable high 60 120 140 ns
t
WHQX
WRITE enable high to output transition 5 10 10 ns
