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LPC2105FBD48/01,15

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
LPC2104_2105_2106_7 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 07 — 20 June 2008 16 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.9 General purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back, as well as the current state of the port pins.
6.9.1 Features
• Direction control of individual bits.
• Separate control of output set and clear.
• All I/O default to inputs after reset.
6.9.2 Features added with the Fast GPIO set of registers available on
LPC2104/2105/2106/01 only
• Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O
timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.
• Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
• All Fast GPIO registers are byte addressable.
• Entire port value can be written in one instruction.
• Ports are accessible via either the legacy group of registers (GPIOs) or the group of
registers providing accelerated port access (Fast GPIOs).
6.10 UARTs
The LPC2104/2105/2106 each contain two UARTs. One UART provides a full modem
control handshake interface, the other provides only transmit and receive data lines.
6.10.1 Features
• 16 byte Receive and Transmit FIFOs
• Register locations conform to 16C550 industry standard
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B
• Built-in baud rate generator
25:24 P0.28 0 0 GPIO Port 0.28 0
0 1 TMS
27:26 P0.29 0 0 GPIO Port 0.29 0
0 1 TCK
29:28 P0.30 0 0 GPIO Port 0.30 0
0 1 TDI
31:30 P0.31 0 0 GPIO Port 0.31 0
0 1 TDO
Table 7. Pin function select register 1 (PINSEL1 - 0xE002 C004)
…continued
PINSEL1 Pin name Value Function Value after
reset
LPC2104_2105_2106_7 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 07 — 20 June 2008 17 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
• Standard modem interface signals included on UART 1.
6.10.2 UART features available in LPC2104/2105/2106/01 only
Compared to previous LPC2000 microcontrollers, UARTs in LPC2104/2105/2106/01
introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers
to achieve standard baud rates such as 115200 Bd with any crystal frequency above
2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in
hardware.
• Fractional baud rate generator enables standard baud rates such as 115200 Bd to be
achieved with any crystal frequency above 2 MHz.
• Autobauding.
• Auto-CTS/RTS flow-control fully implemented in hardware.
6.11 I
2
C-bus serial I/O controller
I
2
C is a bidirectional bus for inter-IC control using only two wires: a serial clock line (SCL),
and a serial data line (SDA). Each device is recognized by a unique address and can
operate as either a receiver-only device (e.g. an LCD driver or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. I
2
C is a multi-master bus, it can be
controlled by more than one bus master connected to it.
The I
2
C-bus implemented in LPC2104/2105/2106 supports bit rate up to 400 kbit/s (Fast
I
2
C-bus).
6.11.1 Features
• Standard I
2
C compliant bus interface.
• Easy to configure as Master, Slave or Master/Slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I
2
C-bus may be used for test and diagnostic purposes.
LPC2104_2105_2106_7 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 07 — 20 June 2008 18 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.12 SPI serial I/O controller
The SPI is a full duplex serial interface, designed to be able to handle multiple masters
and slaves connected to a given bus. Only a single master and a single slave can
communicate on the interface during a given data transfer. During a data transfer the
master always sends a byte of data to the slave, and the slave always sends a byte of data
to the master.
6.12.1 Features
• Compliant with Serial Peripheral Interface (SPI) specification.
• Synchronous, serial, full duplex communication.
• Combined SPI master and slave.
• Maximum data bit rate of one eighth of the input clock rate.
6.12.2 Features available in LPC2104/2105/2106/01 only
• Selectable transfer width of eight to 16 bit per frame.
• When the SPI interface is used in Master mode, the SSEL pin is not needed (can be
used for a different function).
6.13 SSP controller (LPC2104/2015/2106/01 only)
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. Data transfers are in
principle full duplex, with frames of four to 16 bits of data flowing from the master to the
slave and from the slave to the master.
Because the SSP and SPI peripherals share the same physical pins, it is not possible to
have both of these two peripherals active at the same time. Application can switch on the
fly from SPI to SSP and back.
6.13.1 Features
• Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National
Semiconductor’s Microwire buses.
• Synchronous serial communication.
• Master or slave operation.
• 8-frame FIFOs for both transmit and receive.
• Four to 16 bits per frame.
6.14 General purpose timers
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. It also includes up to four capture inputs to trap the timer value when an
input signal transitions, optionally generating an interrupt.
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LPC2105FBD48/01,15

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Buy LPC2105FBD48/01,15
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU ARM Microcontrollers - MCU 128K FL/32K RAM/2 UART/I2C/SPI
Lifecycle:
New from this manufacturer.
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