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MAX1295BEEI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
______________________________________________________________________________________ 13
External Clock Mode
To select the external clock mode, bits D6 and D7 of
the control byte must be set to 1. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. For proper operation, a 100kHz to
4.8MHz clock frequency with 30% to 70% duty cycle is
recommended. Operating the MAX1295/MAX1297 with
clock frequencies lower than 100kHz is not recommend-
ed because the resulting voltage droop across the hold
capacitor in the T/H stage degrades performance.
Digital Interface
The input and output data are multiplexed on a three-
state parallel interface (I/O) that can easily be inter-
faced with standard µPs. The signals CS, WR, and RD
control the write and read operations. CS represents
Figure 6a. External Clock and
WR
Timing (Internal Acquisition Mode)
Figure 6b. External Clock and
WR
Timing (External Acquisition Mode)
WR
CLK
CLK
WR
WR GOES HIGH WHEN CLK IS HIGH.
WR GOES HIGH WHEN CLK IS LOW.
t
CWS
t
CH
t
CL
t
CP
t
CWH
ACQUISITION STARTS
ACQUISITION STARTS
CONVERSION STARTS
CONVERSION STARTS
ACQUISITION ENDS
ACQUISITION ENDS
ACQMOD = "0"
ACQMOD = "0"
WR
CLK
CLK
WR
WR GOES HIGH WHEN CLK IS HIGH
WR GOES HIGH WHEN CLK IS LOW
t
DH
t
DH
t
CWH
t
CWS
ACQUISITION STARTS
ACQUISITION STARTS
CONVERSION STARTS
CONVERSION STARTS
ACQUISITION ENDS
ACQUISITION ENDS
ACQMOD = "1"
ACQMOD = "1"
ACQMOD = "0"
ACQMOD = "0"
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
14 ______________________________________________________________________________________
the chip-select signal, which enables a µP to address
the MAX1295/MAX1297 as an I/O port. When high, CS
disables the CLK, WR, and RD inputs and forces the
interface into a high-impedance (high-Z) state.
Input Format
The control bit sequence is latched into the device on
pins D7–D0 during a write command. Table 4 shows
the control-byte format.
Output Data Format
The 12-bit-wide output format for both the MAX1295/
MAX1297 is binary in unipolar mode and two’s comple-
ment in bipolar mode. CS, RD, WR, INT, and the 12 bits
of output data can interface directly to a 16-bit data bus.
When reading the output data, CS and RD must be low.
__________Applications Information
Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1295/MAX1297 in external clock
mode and sets INT high. After the power supplies stabi-
lize, the internal reset time is 10µs; no conversions
should be attempted during this phase. When using the
internal reference, 500µs is required for V
REF
to stabilize.
Internal and External Reference
The MAX1295/MAX1297 can be used with an internal
or external reference voltage. An external reference
can be connected directly to REF or REFADJ.
An internal buffer is designed to provide +2.5V at REF for
both the MAX1295 and MAX1297. The internally trimmed
+1.22V reference is buffered with a +2.05V/V gain.
Internal Reference
The full-scale range with the internal reference is +2.5V
with unipolar inputs and ±1.25V with bipolar inputs. The
internal reference buffer allows for small adjustments
(±100mV) in the reference voltage (Figure 7).
Note: The reference buffer must be compensated with
an external capacitor (4.7µF min) connected between
REF and GND to reduce reference noise and switching
spikes from the ADC. To further minimize noise on the
reference, connect a 0.01µF capacitor between REFADJ
and GND.
External Reference
With both the MAX1295 and MAX1297, an external refer-
ence can be placed at either the input (REFADJ) or the
output (REF) of the internal reference buffer amplifier.
Using the REFADJ input makes buffering the external
reference unnecessary. The REFADJ input impedance
is typically 17kΩ.
When applying an external reference to REF, disable
the internal reference buffer by connecting REFADJ to
V
DD
. The DC input resistance at REF is 25kΩ.
Therefore, an external reference at REF must deliver up
to 200µA DC load current during a conversion and
have an output impedance less than 10Ω. If the refer-
ence has higher output impedance or is noisy, bypass
it close to the REF pin with a 4.7µF capacitor.
Power-Down Modes
To save power, place the converter in a low-current
shutdown state between conversions. Select standby
mode or shutdown mode using bits D6 and D7 of the
control byte (Tables 1 and 4). In both software power-
down modes, the parallel interface remains active, but
the ADC does not convert.
Standby Mode
While in standby mode, the supply current is typically
850µA. The part powers up on the next rising edge of
WR and is ready to perform conversions. This quick
turn-on time allows the user to realize significantly
reduced power consumption for conversion rates
below 265ksps.
D6 D4D5
PD0
SGL/DIF
ACQMOD A2 A0A1
D2
D0
(LSB)
UNI/BIP
PD1
D1D3
D7
(MSB)
Table 4. Control-Byte Format
Figure 7. Reference Adjustment with External Potentiometer
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
______________________________________________________________________________________ 15
Shutdown Mode
Shutdown mode turns off all chip functions that draw qui-
escent current, reducing the typical supply current to
2µA immediately after the current conversion is complet-
ed. A rising edge on WR causes the MAX1295/MAX1297
to exit shutdown mode and return to normal operation.
To achieve full 12-bit accuracy with a 4.7µF reference
bypass capacitor, 50µs is required after power-up.
Waiting 50µs in standby mode, instead of in full-power
mode, can reduce power consumption by a factor of 3 or
more. When using an external reference, only 50µs is
required after power-up. Enter standby mode by per-
forming a dummy conversion with the control byte speci-
fying standby mode.
Note: Bypass capacitors larger than 4.7µF between
REF and GND result in longer power-up delays.
Transfer Function
Table 5 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figure 8 depicts the nominal unipo-
lar input/output (I/O) transfer function, and Figure 9
shows the bipolar I/O transfer function. Code transitions
occur halfway between successive-integer LSB values.
Output coding is binary, with 1 LSB = (V
REF
/ 4096).
Maximum Sampling Rate/
Achieving 300ksps
When running at the maximum clock frequency of
4.8MHz, the specified throughput of 265ksps is achieved
by completing a conversion every 18 clock cycles: 1
write cycle, 3 acquisition cycles, 13 conversion cycles,
and 1 read cycle. This assumes that the results of the
last conversion are read before the next control byte is
written. It is possible to achieve higher throughputs, up
to 300ksps, by first writing a control byte to begin the
Table 5. Full-Scale and Zero-Scale for Unipolar and Bipolar Operation
UNIPOLAR MODE BIPOLAR MODE
COM COMZero ScaleZero Scale
V
REF
+ COM
V
REF
/2 + COMPositive Full Scale
Full Scale
-V
REF
/2 + COM Negative Full Scale
Figure 8. Unipolar Transfer Function
Figure 9. Bipolar Transfer Function
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

MAX1295BEEI

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IC ADC 12-BIT 265KSPS 28-QSOP
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