MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
16 ______________________________________________________________________________________
acquisition cycle of the next conversion, and then read-
ing the results of the previous conversion from the bus.
This technique (Figure 10) allows a conversion to be
completed every 16 clock cycles. Note that the switch-
ing of the data bus during acquisition or conversion can
cause additional supply noise, which can make it diffi-
cult to achieve true 12-bit performance.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and don’t lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one star point (Figure 11) connecting the two ground
systems (analog and digital). For lowest noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply, V
DD
, could
impair operation of the ADC’s fast comparator. Bypass
V
DD
to the star ground with a network of two parallel
capacitors, 0.1µF and 4.7µF, located as close as to the
MAX1295/MAX1297’s power-supply pin as possible.
Minimize capacitor lead length for best supply-noise
rejection and add an attenuation resistor (5) if the
power supply is extremely noisy.
Figure 11. Power-Supply and Grounding Connections
Figure 10. Timing Diagram for Fastest Conversion
CLK
ACQUISITION
CONTROL WORD
CONVERSION
D11–D0
ACQUISITION
SAMPLING INSTANT
123 4 5 6 78910111213141516
WR
RD
D7–D0
STATE
CONTROL
WORD
D11–
D0
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
______________________________________________________________________________________ 17
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1295/MAX1297 is measured using the end-
point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (t
AJ
) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (t
AD
) is the time between the rising
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution,
(N Bits):
SNR = (6.02 × N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD (dB) = 20 × log (Signal
RMS
/ Noise
RMS
)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest distor-
tion component.
THD V V V V V log / + + +
20
2
2
3
2
4
2
5
2
1
Chip Information
TRANSISTOR COUNT: 5781
SUBSTRATE CONNECTED TO GND
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
18 ______________________________________________________________________________________
Typical Operating Circuits
V
DD
REF
REFADJ
INT
CH5
CH4
CH3
CH2
CH1
CH0
COM
GND
4.7µF
0.1µF
+3V
+2.5V
OUTPUT STATUS
µP
CONTROL
INPUTS
CLK
CS
WR
RD
D7
D6
D5
D4
D3
D2
D1
D0
µP DATA BUS
D8
D9
D10
D11
ANALOG
INPUTS
MAX1295
V
DD
REF
REFADJ
INT
CH1
CH0
COM
GND
4.7µF
0.1µF
+3V
+2.5V
OUTPUT STATUS
µP
CONTROL
INPUTS
CLK
CS
WR
RD
D7
D6
D5
D4
D3
D2
D1
D0
µP DATA BUS
D8
D9
D10
D11
ANALOG
INPUTS
MAX1297
Pin Configurations (continued)

MAX1295BEEI

Mfr. #:
Manufacturer:
Description:
IC ADC 12-BIT 265KSPS 28-QSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union