EVAL-AD5063EBZ Datasheet AD5063BRMZ, AD5063BRMZ-1, AD5063BRMZ-1-REEL7 | P16-P18

AD5063

Rev. C | Page 15 of 20

AD5063 to 68HC11/68L11 Interface

Figure 32 shows a serial interface between the AD5063 and the

68HC11/68L11 microcontroller. SCK of the 68HC11/68L11

drives the SCLK pin of the AD5063, and the MOSI output

drives the serial data line of the DAC. The

SYNC

signal is

derived from a port line (PC7). The setup conditions for correct

operation of this interface require that the 68HC11/68L11 be

configured so that its CPOL bit is 0 and its CPHA bit is 1. When

data is being transmitted to the DAC, the

SYNC

line is taken

low (PC7). When the 68HC11/68L11 are configured with their

CPOL bit set to 0 and their CPHA bit set to 1, data appearing

on the MOSI output is valid on the falling edge of SCK. Serial

data from the 68HC11/68L11 is transmitted in 8-bit bytes with

only eight falling clock edges occurring in the transmit cycle.

Data is transmitted MSB first. To load data to the AD5063, PC7

is left low after the first eight bits are transferred, and then a

second serial write operation is performed to the DAC, with

PC7 taken high at the end of this procedure.

AD5063

ADDITIONAL PINS OMITTED FOR CLARITY

PC7

SCK

MOSI

SYNC

SCLK

DIN

04766-032

68HC11/

68L11

Figure 32. AD5063 to 68HC11/68L11 Interface

AD5063 to Blackfin® ADSP-BF53x Interface

Figure 33 shows a serial interface between the AD5063 and

the Blackfin® ADSP-BF53x microprocessor. The ADSP-BF53x

processor family incorporates two dual-channel synchronous

serial ports, SPORT1 and SPORT0, for serial and multiprocessor

communications. Using SPORT0 to connect to the AD5063, the

setup for the interface is as follows: DT0PRI drives the DIN pin

of the AD5063, TSCLK0 drives the SCLK of the part, and TFS0

drives

SYNC

ADSP-BF53x

AD5063

ADDITIONAL PINS OMITTED FOR CLARITY

DT0PRI

TSCLK0

TFS0

DIN

SCLK

SYNC

04766-033

Figure 33. AD5063 to Blackfin ADSP-BF53x Interface

AD5063 to 80C51/80L51 Interface

Figure 34 shows a serial interface between the AD5063 and the

80C51/80L51 microcontroller. The setup for the interface is as

follows: TxD of the 80C51/80L51 drives SCLK of the AD5063,

and RxD drives the serial data line of the part. The

SYNC

signal

is again derived from a bit-programmable pin on the port. In

this case, Port Line P3.3 is used. When data is to be transmitted

to the AD5063, P3.3 is taken low. The 80C51/80L51 transmits

data only in 8-bit bytes; therefore, only eight falling clock edges

occur in the transmit cycle. To load data to the DAC, P3.3 is left

low after the first eight bits are transmitted, and a second write

cycle is initiated to transmit the second byte of data. P3.3 is taken

high following the completion of this cycle. The 80C51/80L51

output the serial data in a format that has the LSB first. The

AD5063 requires its data with the MSB as the first bit received.

The 80C51/80L51 transmit routine should take this into

account.

80C51/80L51

AD5063

ADDITIONAL PINS OMITTED FOR CLARITY

P3.3

TxD

RxD

SYNC

SCLK

DIN

04766-034

Figure 34. AD5063 to 80C51/80L51 Interface

AD5063 to MICROWIRE Interface

Figure 35 shows an interface between the AD5063 and any

MICROWIRE-compatible device. Serial data is shifted out on

the falling edge of the serial clock and clocked into the AD5063

on the rising edge of the SK.

MICROWIRE

AD5063

ADDITIONAL PINS OMITTED FOR CLARITY

SYNC

SCLK

DIN

04766-035

Figure 35. AD5063 to MICROWIRE Interface

AD5063

Rev. C | Page 16 of 20

APPLICATIONS

Table 7. Recommended Precision References for the AD5063

Part No.

Initial

Accuracy

(mV max)

Temperature Drift

(ppm/°C max)

CHOOSING A REFERENCE FOR THE AD5063

To achieve optimum performance of the AD5063, thought

should be given to the choice of a precision voltage reference.

The AD5063 has one reference input, V

REF

. The voltage on the

reference input is used to supply the positive input to the DAC;

therefore, any error in the reference is reflected in the DAC.

0.1 Hz to 10 Hz

Noise (μV p-p typ)

ADR435 ±2 3 (R-8) 8

ADR425 ±2 3 (R-8) 3.4

ADR02 ±3 3 (R-8)

ADR02 ±3 3 (SC-70)

There are four possible sources of error when choosing a voltage

reference for high accuracy applications: initial accuracy, ppm

drift, long-term drift, and output voltage noise. Initial accuracy

on the output voltage of the DAC leads to a full-scale error in the

DAC. To minimize these errors, a reference with high initial

accuracy is preferred. Also, choosing a reference with an output

trim adjustment, such as the ADR423, allows a system designer to

trim out system errors by setting a reference voltage to a voltage

other than the nominal. The trim adjustment can also be used at

any point within the operating temperature range to trim out error.

ADR395 ±5 9 (TSOT-23) 8

BIPOLAR OPERATION USING THE AD5063

The AD5063 has been designed for single-supply operation, but

a bipolar output range is also possible by using the circuit shown

in Figure 37. This circuit yields an output voltage range of ±4.096 V.

Rail-to-rail operation at the amplifier output is achievable using

AD8675/AD8031/AD8032 or an OP196.

The output voltage for any input code can be calculated as

Because the supply current required by the AD5063 is extremely

low, the parts are ideal for low supply applications. The ADR395

voltage reference is recommended; it requires less than 100 μA of

quiescent current and can, therefore, drive multiple DACs in one

system, if required. It also provides very good noise performance

at 8 μV p-p in the 0.1 Hz to 10 Hz range.

⎥

⎦

⎤

⎢

⎣

⎡

⎟

⎠

⎞

⎜

⎝

⎛

×−

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

×=

R2R1D

DDDD

536,65

where D represents the input code in decimal (0 to 65,536).

With V

REF

= 5 V, R1 = R2 = 30 kΩ

AD5063

3-WIRE

SERIAL

INTERFACE

SYNC

SCLK

DIN

OUT

= 0V TO 5V

ADR395

04766-036

65536

−

⎟

⎠

⎞

⎜

⎝

⎛

This is an output voltage range of ±5 V, with 0x0000 corresponding

to a −5 V output and 0xFFFF corresponding to a +5 V output.

04766-037

AD5063

DACGND

REF

OUT

SCLK

DIN

SYNC

+5V

+4.096

EXTERNAL

OP A

BIPOLAR

OUTPUT

SERIAL

INTERFACE

0.1

INV

+5V

–5V

AGND

Figure 36. ADR395 as a Reference to AD5063

Long-term drift is a measure of how much the reference drifts

over time. A reference with a tight long-term drift specification

ensures that the overall solution remains relatively stable during

its entire lifetime. The temperature coefficient of a reference’s

output voltage affects INL, DNL, and TUE. A reference with a

tight temperature coefficient specification should be chosen to

reduce the temperature dependence of the DAC output voltage

on ambient conditions.

Figure 37. Bipolar Operation

In high accuracy applications, which have a relatively low

tolerance for noise, reference output voltage noise needs to be

considered. It is important to choose a reference with as low an

output noise voltage as practical for the system noise resolution

required. Precision voltage references, such as the ADR435,

produce low output noise in the 0.1 Hz to 10 Hz region. Exam-

ples of some recommended precision references for use as the

supply to the AD5063 are shown in Table 7.

AD5063

Rev. C | Page 17 of 20

USING THE AD5063 WITH A GALVANICALLY

ISOLATED INTERFACE CHIP

In process-control applications in industrial environments, it is

often necessary to use a galvanically isolated interface to protect

and isolate the controlling circuitry from hazardous common-

mode voltages that may occur in the area where the DAC is

functioning. iCoupler® provides isolation in excess of 2.5 kV.

Because the AD5063 uses a 3-wire serial logic interface, the

ADuM130x family provides an ideal digital solution for the

DAC interface.

The ADuM130x isolators provide three independent isolation

channels in a variety of channel configurations and data rates.

They operate across the full range of 2.7 V to 5.5 V, providing

compatibility with lower voltage systems as well as enabling a

voltage translation functionality across the isolation barrier.

Figure 38 shows a typical galvanically isolated configuration

using the AD5063. The power supply to the part also needs to

be isolated; this is accomplished by using a transformer. On the

DAC side of the transformer, a 5 V regulator provides the 5 V

supply required for the AD5063.

AD5063ADMu1300

POWER 10µF 0.1µF

GND

REGULATOR

SCLKV0A

OUTV0B SYNC

V0C

V1A

V1B

V1C

SCLK

SDI

DAT

A DIN

04766-039

Figure 38. AD5063 with a Galvanically Isolated Interface

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to consider

carefully the power supply and ground return layout on the

board. The printed circuit board containing the AD5063 should

have separate analog and digital sections, each on its own area

of the board. If the AD5063 is in a system where other devices

require an AGND-to-DGND connection, the connection

should be made at one point only. This ground point should be

as close as possible to the AD5063.

The power supply to the AD5063 should be bypassed with

10 μF and 0.1 μF capacitors. The capacitors should physically be

as close as possible to the device, with the 0.1 μF capacitor

ideally right up against the device. The 10 μF capacitors are the

tantalum bead type. It is important that the 0.1 μF capacitor has

low effective series resistance (ESR) and low effective series

inductance (ESI), as do common ceramic types of capacitors.

This 0.1 μF capacitor provides a low impedance path to ground

for high frequencies caused by transient currents from internal

logic switching.

The power supply line itself should have as large a trace as

possible to provide a low impedance path and to reduce glitch

effects on the supply line. Clocks and other fast switching

digital signals should be shielded from other parts of the board

by a digital ground. Avoid crossover of digital and analog

signals, if possible. When traces cross on opposite sides of the

board, ensure that they run at right angles to each other to

reduce feedthrough effects on the board. The best board layout

technique is the microstrip technique where the component

side of the board is dedicated to the ground plane only, and the

signal traces are placed on the solder side. However, this is not

always possible with a 2-layer board.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

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AD5063 DAC Evaluation Board

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