AD5063
Rev. C | Page 3 of 20
SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V, V
REF
= 4.096 V @ V
DD
= 5.0 V, R
L
= unloaded, C
L
= unloaded to GND; T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
B Version
1
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 16 Bits
Relative Accuracy (INL) ±0.5 ±1 LSB −40°C to + 85°C, B grade over all codes
Total Unadjusted Error (TUE) ±500 ±800 μV
Differential Nonlinearity (DNL) ±0.5 ±1 LSB Guaranteed monotonic
Gain Error ±0.01 ±0.02 % FSR T
A
= −40°C to +85°C
Gain Error Temperature Coefficient 1 ppm FSR/°C
Zero-Code Error ±0.05 ±0.1 mV
All 0s loaded to DAC register,
T
A
= −40°C to +85°C
Zero-Code Error Temperature Coefficient 0.05 μV/°C
Offset Error ±0.05 ±0.1 mV T
A
= −40°C to +85°C
Offset Error Temperature Coefficient 0.5 μV/°C
Full-Scale Error ±500 ±800 μV
All 1s loaded to DAC register,
T
A
= −40°C to +85°C
Bipolar Resistor Matching 1 Ω/Ω R
FB
/R
INV
, R
FB
= R
INV
= 30 kΩ typically
Bipolar Zero Offset Error ±8 ±16 LSB
Bipolar Zero Temperature Coefficient ±0.5 ppm FSR/°C
Bipolar Gain Error ±16 ±32 LSB
OUTPUT CHARACTERISTICS
2
Output Voltage Range 0 V
REF
V Unipolar operation
−V
REF
V
REF
V Bipolar operation
Output Voltage Settling Time
3
¼ scale to ¾ scale code transition to ±1 LSB
AD5063BRMZ 4 μs
AD5063BRMZ-1 1 μs V
DD
= 4.5 V to 5.5 V
4 μs V
DD
= 2.7 V to 5.5 V
Output Noise Spectral Density 64 nV/√Hz DAC code = midscale, 1 kHz
Output Voltage Noise 6 μV p-p
DAC code = midscale, 0.1 Hz to 10 Hz
bandwidth
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry
Digital Feedthrough 0.002 nV-s
DC Output Impedance (Normal) 8 Output impedance tolerance ±10%
DC Output Impedance (Power-Down)
(Output Connected to 1 kΩ Network) 1 Output impedance tolerance ±400 Ω
(Output Connected to 10 kΩ Network) 100 Output impedance tolerance ±20 kΩ
REFERENCE INPUT/OUPUT
V
REF
Input Range 2 V
DD
− 50 mV
Input Current (Power-Down) ±1 μA Zero-scale loaded
Input Current (Normal) ±1 μA
DC Input Impedance 1 Bipolar/unipolar operation
LOGIC INPUTS
Input Current
4
±1 ±2 μA
Input Low Voltage, V
IL
0.8 V V
DD
= 4.5 V to 5.5 V
0.8 V
DD
= 2.7 V to 3.6 V
Input High Voltage, V
IH
2.0 V V
DD
= 2.7 V to 5.5 V
1.8 V
DD
= 2.7 V to 3.6 V
Pin Capacitance 4 pF
AD5063
Rev. C | Page 4 of 20
B Version
1
Parameter Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS
V
DD
2.7 5.5 V All digital inputs at 0 V or V
DD
I
DD
(Normal Mode) DAC active and excluding load current
V
DD
= 4.5 V to 5.5 V 0.65 0.7 mA
V
IN
= V
DD
and V
IL
= GND, V
DD
= 5 V,
V
REF
= 4.096 V, code = midscale
V
DD
= 2.7 V to 3.6 V 0.5 mA V
IH
= V
DD
and V
IL
= GND, V
DD
= 3 V
I
DD
(All Power-Down Modes)
V
DD
= 4.5 V to 5.5 V 1 μA V
IH
= V
DD
and V
IL
= GND
V
DD
= 2.7 V to 3.6 V 1 μA V
IH
= V
DD
and V
IL
= GND
Power Supply Rejection Ratio (PSRR) 0.5 LSB ∆V
DD
± 10%, V
DD
= 5 V, unloaded
1
Temperature ranges for the B version: −40°C to +85°C, typical at +25°C, functional to +125°C.
2
Guaranteed by design and characterization, not production tested.
3
See the Ordering Guide.
4
Total current flowing into all pins.
AD5063
Rev. C | Page 5 of 20
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Limit
1
Unit Test Conditions/Comments
t
1
2
33 ns min SCLK cycle time
t
2
5 ns min SCLK high time
t
3
3 ns min SCLK low time
t
4
10 ns min
SYNC
to SCLK falling edge setup time
t
5
3 ns min Data setup time
t
6
2 ns min Data hold time
t
7
0 ns min
SCLK falling edge to SYNC
rising edge
t
8
12 ns min
Minimum SYNC
high time
t
9
9 ns min
SYNC
rising edge to next SCLK fall ignore
1
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Maximum SCLK frequency is 30 MHz.
t
4
t
3
t
2
t
5
t
7
t
6
D0D1D2D22D23
SYNC
SCLK
04766-002
t
9
t
1
t
8
D23 D22
DIN
Figure 2. Timing Diagram

EVAL-AD5063EBZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
AD5063 DAC Evaluation Board
Lifecycle:
New from this manufacturer.
Delivery:
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