NCV3030ADR2G Datasheet NCP3030BDR2G, NCV3030BDR2G, NCV3030ADR2G | P19-P21

NCP3030A, NCP3030B, NCV3030A, NCV3030B

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19

where:

t

ON

+

Q

GD

I

G1

+

Q

GD

ǒ

V

BST

* V

TH

Ǔ

ń

ǒ

R

HSPU

) R

G

Ǔ

(eq. 29)

and:

t

OFF

+

Q

GD

I

G2

+

Q

GD

ǒ

V

BST

* V

TH

Ǔ

ń

ǒ

R

HSPD

) R

G

Ǔ

(eq. 30)

Next, the MOSFET output capacitance losses are caused

by both the control and synchronous MOSFET but are

dissipated only in the control MOSFET.

P

DS

+

1

2

@ Q

OSS

@ V

IN

@ f

SW

(eq. 31)

Finally the loss due to the reverse recovery time of the

body diode in the synchronous MOSFET is shown as

follows:

P

RR

+ Q

RR

@ V

IN

@ f

SW

(eq. 32)

The low−side or synchronous MOSFET turns on into zero

volts so switching losses are negligible. Its power

dissipation only consists of conduction loss due to R

DS(on)

and body diode loss during the non−overlap periods.

P

D_SYNC

+ P

COND

) P

BODY

(eq. 33)

Conduction loss in the low−side or synchronous

MOSFET is described as follows:

P

COND

+

ǒ

I

RMS_SYNC

Ǔ

2

@ R

DS(on)_SYNC

(eq. 34)

where:

(eq. 35)

I

RMS_SYNC

+ I

OUT

@

(

1 * D

)

@

ǒ

1 )

ǒ

ra

2

12

Ǔ

Ǹ

The body diode losses can be approximated as:

P

BODY

+ V

FD

@ I

OUT

@ f

SW

@

ǒ

NOL

LH

) NOL

HL

Ǔ

(eq. 36)

Vth

Figure 32. MOSFET Switching Characteristics

I

G1

: output current from the high−side gate drive (HSDR)

I

G2

: output current from the low−side gate drive (LSDR)

ƒ

SW

: switching frequency of the converter. NCP3030A is

1.2 MHz and NCP3030B is 2.4 MHz

V

BST

: gate drive voltage for the high−side drive, typically

7.5 V.

Q

GD

: gate charge plateau region, commonly specified in the

MOSFET datasheet

V

TH

: gate−to−source voltage at the gate charge plateau

region

Q

OSS

: MOSFET output gate charge specified in the data

sheet

Q

RR

: reverse recovery charge of the low−side or

synchronous MOSFET, specified in the datasheet

R

DS(on)_CONTROL

: on resistance of the high−side, or

control, MOSFET

R

DS(on)_SYNC

: on resistance of the low−side, or

synchronous, MOSFET

NOL

LH

: dead time between the LSDR turning off and the

HSDR turning on, typically 85 ns

NOL

HL

: dead time between the HSDR turning off and the

LSDR turning on, typically 75 ns

Once the MOSFET power dissipations are determined,

the designer can calculate the required thermal impedance

for each device to maintain a specified junction temperature

at the worst case ambient temperature. The formula for

calculating the junction temperature with the package in free

air is:

T

J

+ T

A

) P

D

@ R

qJA

T

J

: Junction Temperature

T

A

: Ambient Temperature

P

D

: Power Dissipation of the MOSFET under analysis

R

q

JA

: Thermal Resistance Junction−to−Ambient of the

MOSFET’s package

As with any power design, proper laboratory testing

should be performed to insure the design will dissipate the

required power under worst case operating conditions.

Variables considered during testing should include

maximum ambient temperature, minimum airflow,

maximum input voltage, maximum loading, and component

variations (i.e. worst case MOSFET R

DS(on)

).

NCP3030A, NCP3030B, NCV3030A, NCV3030B

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20

Figure 33. MOSFETs Timing Diagram

High−Side

Logic Signal

Low−Side

Logic Signal

High−Side

MOSFET

Low−Side

MOSFET

R

DSmax

R

DS(on)min

R

DSmax

R

DS(on)min

NOL

HL

NOL

LH

t

f

t

d(on)

t

r

t

d(off)

t

r

t

f

t

d(on)

t

d(off)

Another consideration during MOSFET selection is their

delay times. Turn−on and turn−off times must be short

enough to prevent cross conduction. If not, there will be

conduction from the input through both MOSFETs to

ground. Therefore, the following conditions must be met.

t

d(ON)_CONTROL

) NOL

LH

u t

d(OFF)_SYNC

) t

f_SYNC

(eq. 37)

t

(ON)_SYNC

) NOL

HL

u t

d(OFF)_CONTROL

) t

f

_CONTROL

and

The MOSFET parameters, t

d(ON)

, t

r

, t

d(OFF)

and t

f

are can

be found in their appropriate datasheets for specific

conditions. NOL

LH

and NOL

HL

are the dead times which

were described earlier and are 85 ns and 75 ns, respectively.

Feedback and Compensation

The NCP3030 is a voltage mode buck convertor with a

transconductance error amplifier compensated by an

external compensation network. Compensation is needed to

achieve accurate output voltage regulation and fast transient

response. The goal of the compensation circuit is to provide

a loop gain function with the highest crossing frequency and

adequate phase margin (minimally 45°). The transfer

function of the power stage (the output LC filter) is a double

pole system. The resonance frequency of this filter is

expressed as follows:

f

P0

+

1

2 @ p @ L @ C

OUT

Ǹ

(eq. 38)

Parasitic Equivalent Series Resistance (ESR) of the

output filter capacitor introduces a high frequency zero to

the filter network. Its value can be calculated by using the

following equation:

f

Z0

+

1

2 @ p @ C

OUT

@ ESR

(eq. 39)

The main loop zero crossover frequency f0 can be chosen

to be 1/10 − 1/5 of the switching frequency. Table 2 shows

the three methods of compensation.

Table 2. COMPENSATION TYPES

Zero Crossover Frequency Condition Compensation Type Typical Output Capacitor Type

f

P0

< f

Z0

< f

0

< f

S

/2 Type II Electrolytic, Tantalum

f

P0

< f

0

< f

Z0

< f

S

/2 Type III Method I Tantalum, Ceramic

f

P0

< f

0

< f

S

/2 < f

Z0

Type III Method II Ceramic

NCP3030A, NCP3030B, NCV3030A, NCV3030B

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21

Compensation Type II

This compensation is suitable for electrolytic capacitors.

Components of the Type II (Figure 34) network can be

specified by the following equations:

Figure 34. Type II Compensation

R

C1

+

2 @ p @ f

0

@ L @ V

RAMP

@ V

OUT

ESR @ V

IN

@ V

ref

@ gm

(eq. 40)

C

C1

+

1

0.75 @ 2 @ p @ f

P0

@ R

C1

(eq. 41)

C

C2

+

1

p @ R

C1

@ f

S

(eq. 42)

R1 +

V

OUT

* V

ref

V

ref

@ R2

(eq. 43)

V

RAMP

is the peak−to−peak voltage of the oscillator ramp

and gm is the transconductance error amplifier gain.

Capacitor C

C2 is optional.

Compensation Type III

Tantalum and ceramics capacitors have lower ESR than

electrolytic, so the zero of the output LC filter goes to a

higher frequency above the zero crossover frequency. This

requires a Type III compensation network as shown in

Figure 35.

There are two methods to select the zeros and poles of this

compensation network. Method I is ideal for tantalum

output capacitors, which have a higher ESR than ceramic:

Figure 35. Type III Compensation

f

Z1

+ 0.75 @ f

P0

(eq. 44)

f

Z2

+ f

P0

(eq. 45)

f

P2

+ f

Z0

(eq. 46)

f

P3

+

f

S

2

(eq. 47)

Method II is better suited for ceramic capacitors that

typically have the lowest ESR available:

f

Z2

+ f

0

@

1 * sinq max

1 ) sinq max

Ǹ

(eq. 48)

f

P2

+ f

0

@

1 ) sinq max

1 * sinq max

Ǹ

(eq. 49)

f

Z1

+ 0.5 @ f

Z2

(eq. 50)

f

P3

+ 0.5 @ f

S

(eq. 51)

The remaining calculations are the same for both methods.

R

C1

uu

2

gm

(eq. 52)

C

C1

+

1

2 @ p @ f

Z1

@ R

C1

(eq. 53)

C

C2

+

1

2 @ p @ f

P3

@ R

C1

(eq. 54)

C

FB1

+

2 @ p @ f

0

@ L @ V

RAMP

@ C

OUT

V

IN

@ R

C1

(eq. 55)

R

FB1

+

1

2p @ C

FB1

@ f

P2

(eq. 56)

R1 +

1

2 @ p @ C

FB1

@ f

Z2

* R

FB1

(eq. 57)

R2 +

V

ref

V

OUT

* V

ref

@ R1

(eq. 58)

If the equation in Equation 59 is not true, then a higher value

of R

C1

must be selected.

R1 @ R2 @ R

FB1

R1 @ R

FB1

) R2 @ R

FB1

) R1 @ R2

u

1

gm

(eq. 59)

NCV3030ADR2G

NCV3030ADR2G

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