Serial Input, Voltage Output
12-/14-Bit Digital-to-Analog Converters
AD5530/AD5531
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
Pin-compatible 12-, 14-bit digital-to-analog converters
Serial input, voltage output
Maximum output voltage range of ±10 V
Data readback
3-wire serial interface
Clear function to a user-defined voltage
Power-down function
Serial data output for daisy-chaining
16-lead TSSOP
APPLICATIONS
Industrial automation
Automatic test equipment
Process control
General-purpose instrumentation
FUNCTIONAL BLOCK DIAGRAM
0
0938-001
LDAC
RBEN
REFAGND
SDIN
POWER-DOWN
CONTROL LOGIC
DAC REGISTER
REFIN
12-/14-BIT
DAC
R
R
GND
SCLK SYNC SDO
R
R
V
OUT
DUTGND
V
DD
V
SS
SHIFT REGISTER
AD5530/AD5531
CLR
PD
Figure 1.
GENERAL DESCRIPTION
The AD5530/AD5531 are single 12- and 14-bit (respectively)
serial input, voltage output digital-to-analog converters (DAC).
They utilize a versatile 3-wire interface that is compatible with
SPI®, QSPI™, MICROWIRE™, and DSP interface standards. Data
is presented to the part in a 16-bit serial word format. Serial
data is available on the SDO pin for daisy-chaining purposes.
Data readback allows the user to read the contents of the DAC
register via the SDO pin.
The DAC output is buffered by a gain of two amplifier and
referenced to the potential at DUTGND.
LDAC
can be used to
update the output of the DAC asynchronously. A power-down
pin (
PD
) allows the DAC to be put into a low power state, and
a
CLR
pin allows the output to be cleared to a user-defined
voltage, the potential at DUTGND.
The AD5530/AD5531 are available in 16-lead TSSOP.
AD5530/AD5531
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Performance Characteristics................................................ 5
Standalone Timing Characteristics............................................ 5
Daisy-Chaining and Readback Timing Characteristics.......... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
DAC Architecture....................................................................... 13
Serial Interface ............................................................................ 13
PD
Function................................................................................ 13
Readback Function .................................................................... 13
CLR
Function.............................................................................. 13
Output Voltage............................................................................ 14
Bipolar Configuration................................................................ 14
Microprocessor Interfacing........................................................... 15
AD5530/AD5531 to ADSP-21xx.............................................. 15
AD5530/AD5531 to 8051 Interface ......................................... 15
AD5530/AD5531 to MC68HC11 Interface............................ 15
Applications Information.............................................................. 17
Optocoupler Interface................................................................ 17
Serial Interface to Multiple AD5530s or AD5531s................ 17
Daisy-Chaining Interface with Multiple AD5530s or
AD5531s ...................................................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
1/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Figure 28...................................................................... 17
3/06—Rev. 0 to Rev. A
Change to Table 3 ............................................................................. 5
Change to Figure 4 ........................................................................... 8
Change to Output Voltage Section............................................... 14
Change to Ordering Guide............................................................ 18
5/02—Revision 0: Initial Version
AD5530/AD5531
Rev. B | Page 3 of 20
SPECIFICATIONS
V
DD
= 15 V ± 10%; V
SS
= −15 V ± 10%; GND = 0 V; R
L
= 5 kΩ and C
L
= 220 pF to GND. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
1
AD5530 AD5531 Unit Test Conditions/Comments
ACCURACY
Resolution 12 14 Bits
Relative Accuracy ±1 ±2 LSB max
Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic over temperature
Zero-Scale Error ±2 ±8 LSB max Typically within ±1 LSB
Full-Scale Error ±2 ±8 LSB max Typically within ±1 LSB
Gain Error ±1 ±4 LSB typ
Gain Temperature Coefficient
2
0.5 0.5 ppm FSR/°C typ
10 10 ppm FSR/°C max
REFERENCE INPUTS
2
Reference Input Range 0 to 5 0 to 5 V min to V max Max output range ±10 V
DC Input Resistance 100 100 MΩ typ
Input Current ±1 ±1 μA max Per input, typically ±20 nA
DUTGND INPUT
2
DC Input Impedance 60 60 kΩ typ
Max Input Current ±0.3 ±0.3 mA typ
Input Range −4 to +4 −4 to +4 V min to V max Max output range ±10 V
O/P CHARACTERISTICS
2
Output Voltage Swing ±10 ±10 V max
Short-Circuit Current 15 15 mA max
Resistive Load 5 5 kΩ min To 0 V
Capacitive Load 1200 1200 pF max To 0 V
DC Output Impedance 0.5 0.5 Ω max
DIGITAL I/O
V
INH
, Input High Voltage 2.4 2.4 V min
V
INL
, Input Low Voltage 0.8 0.8 V max
I
INH
, Input Current ±10 ±10 μA max Total for all pins
C
IN
, Input Capacitance
2
10 10 pF max 3 pF typical
SDO V
OL
, Output Low Voltage 0.4 0.4 V max I
SINK
= 1 mA
POWER REQUIREMENTS
V
DD
/V
SS
+15/−15 +15/−15 V nom ±10% for specified performance
Power Supply Sensitivity
ΔFull Scale/ΔV
DD
110 110 dB typ
ΔFull Scale/ΔV
SS
100 100 dB typ
I
DD
2 2 mA max Outputs unloaded
I
SS
2 2 mA max Outputs unloaded
I
DD
in Power-Down 150 150 μA max Typically 50 μA
1
Temperature range for B Version: −40°C to +85°C.
2
Guaranteed by design, not subject to production test.

AD5530BRUZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12-BIT VTG OUTPUT IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union