AD5530/AD5531
Rev. B | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 6.
Parameter Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
V
DD
to GND −0.3 V to +17 V
V
SS
to GND +0.3 V to −17 V
Digital Inputs to GND −0.3 V to V
DD
+ 0.3 V
SDO to GND −0.3 V to +6.5 V
REFIN to REFAGND −0.3 V to +17 V
REFIN to GND V
SS
− 0.3 V to V
DD
+ 0.3 V
ESD CAUTION
REFAGND to GND V
SS
− 0.3 V to V
DD
+ 0.3 V
DUTGND to GND V
SS
− 0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature (T
J MAX
) 150°C
Package Power Dissipation (T
J MAX
– T
A
)/θ
JA
Thermal Impedance θ
JA
TSSOP (RU-16) 150.4°C/W
Lead Temperature (Soldering 10 sec) 300°C
IR Reflow, Peak Temperature (<20 sec) 235°C
AD5530/AD5531
Rev. B | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REFAGND
1
REFIN
2
LDAC
3
SDIN
4
SYNC
5
RBEN
6
SCLK
7
SDO
8
V
DD
16
V
OUT
15
DUTGND
14
V
SS
13
NC
12
GND
11
PD
10
CLR
9
AD5530/
AD5531
TOP VIEW
(Not to Scale)
NC = NO CONNECT
0
0938-004
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1 REFAGND For bipolar ±10 V output range, this pin should be tied to 0 V.
2 REFIN This is the voltage reference input for the DAC. Connect to external 5 V reference for specified bipolar ±10 V output.
3
LDAC Load DAC Logic Input (Active Low). When taken low, the contents of the shift register are transferred to the DAC
register.
LDAC can be tied permanently low, enabling the outputs to be updated on the rising edge of SYNC.
4 SDIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the falling edge of SCLK.
5
SYNC
Active Low Control Input. Data is clocked into the shift register on the falling edges of SCLK.
6
RBEN Active Low Readback Enable Function. This function allows the contents of the DAC register to be read. Data
from the DAC register is shifted out on the SDO pin on each rising edge of SCLK.
7 SCLK Clock Input. Data is clocked into the input register on the falling edge of SCLK.
8 SDO
Serial Data Out. This pin is used to clock out the serial data previously written to the input shift register or can be
used in conjunction with
RBEN to read back the data from the DAC register. This is an open drain output; it
should be pulled high with an external pull-up resistor. In standalone mode, SDO should be tied to GND or left
high impedance.
9
CLR Level Sensitive, Active Low Input. A falling edge of CLR resets V
OUT
to DUTGND. The contents of the registers
are untouched.
10
PD
This allows the DAC to be put into a power-down state.
11 GND Ground Reference.
12 NC Do not connect anything to this pin.
13 V
SS
Negative Analog Supply Voltage. −12 V ± 10% or −15 V ± 10%, for specified performance.
14 DUTGND V
OUT
is referenced to the voltage applied to this pin.
15 V
OUT
DAC Output.
16 V
DD
Positive Analog Supply Voltage. 12 V ± 10% or 15 V ± 10%, for specified performance.
AD5530/AD5531
Rev. B | Page 9 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 500 1000 1500 2000 2500 3000 3500 4000
LSB
CODE
00938-005
V
DD
= +15V
V
SS
= –15V
REFIN = +5V
REFAGND = 0V
T
A
= 25°C
1.00
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
0 2000 4000 6000 8000 10000 12000 14000 16000
LSB
CODE
00938-008
V
DD
= +15V
V
SS
= –15V
REFIN = +5V
REFAGND = 0V
T
A
= 25°C
Figure 5. AD5530 Typical INL Plot Figure 8. AD5531 Typical DNL Plot
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0 500 1000 1500 2000 2500 3000 3500 4000
LSB
CODE
00938-006
V
DD
= +15V
V
SS
= –15V
REFIN = +5V
REFAGND = 0V
T
A
= 25°C
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–40 806040200–20
ERROR (LSB)
TEMPERATURE (°C)
00938-009
V
DD
= +15V
V
SS
= –15V
REFIN = +5V
REFAGND = 0V
Figure 6. AD5530 Typical DNL Plot Figure 9. AD5531 Typical INL Error vs. Temperature
1.0
–1.0
–0.8
–0.6
–0.2
–0.4
0
0.2
0.4
0.6
0.8
–40 806040200–20
ERROR (LSB)
TEMPERATURE (°C)
00938-010
V
DD
= +15V
V
SS
= –15V
REFIN = +5V
REFAGND = 0V
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0 2000 4000 6000 8000 10000 12000 14000 16000
LSB
CODE
00938-007
V
DD
= +15V
V
SS
= –15V
REFIN = +5V
REFAGND = 0V
T
A
= 25°C
Figure 10. AD5531 Typical DNL Error vs. Temperature
Figure 7. AD5531 Typical INL Plot

AD5530BRUZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12-BIT VTG OUTPUT IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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