AD526
REV. D
–8–
THEORY OF OPERATION
The AD526 is a complete software programmable gain amplifier
(SPGA) implemented monolithically with a drift-trimmed
BiFET amplifier, a laser wafer trimmed resistor network, JFET
analog switches and TTL compatible gain code latches.
A particular gain is selected by applying the appropriate gain
code (see Table I) to the control logic. The control logic turns
on the JFET switch that connects the correct tap on the gain
network to the inverting input of the amplifier; all unselected
JFET gain switches are off (open). The “on” resistance of the
gain switches causes negligible gain error since only the
amplifier’s input bias current, which is less than 150 pA, actu-
ally flows through these switches.
The AD526 is capable of storing the gain code, (latched mode),
B, A0, A1, A2, under the direction of control inputs CLK and
CS. Alternatively, the AD526 can respond directly to gain code
changes if the control inputs are tied low (transparent mode).
For gains of 8 and 16, a fraction of the frequency compensation
capacitance (C1 in Figure 32) is automatically switched out of
the circuit. This increases the amplifier’s bandwidth and im-
proves its signal settling time and slew rate.
AMPLIFIER
+V
S
V
IN
N1 N2
C1
C2
OUT
FORCE
OUT
SENSE
–V
S
A0
A1
A2
B
CLK
CS
DIGITAL
GND
L
A
T
C
H
E
S
C
O
N
T
R
O
L
L
O
G
I
C
G = 8
G = 16
ANALOG
GND2
ANALOG
GND1
1kV 1.7kV
G = 2
G = 4
1.7kV
3.4kV
1kV
14kV
RESISTOR
NETWORK
Figure 32. Simplified Schematic of the AD526
TRANSPARENT MODE OF OPERATION
In the transparent mode of operation, the AD526 will respond
directly to level changes at the gain code inputs (A0, A1, A2) if
B is tied high and both CS and CLK are allowed to float low.
After the gain codes are changed, the AD526’s output voltage
typically requires 5.5 µs to settle to within 0.01% of the final
value. Figures 26 to 29 show the performance of the AD526 for
positive gain code changes.
16 15 14 13 12 11 10 9
12345678
+
–
OUT
FORCE
OUT
SENSE
V
OUT
0.1mF
AD526
168421
GAIN NETWORK
A1 A0 CS CLK A2 B
LOGIC AND LATCHES
–V
S
0.1mF
+V
S
+5V
A2
A1
A0
V
IN
Figure 33. Transparent Mode
LATCHED MODE OF OPERATION
The latched mode of operation is shown in Figure 34. When
either CS or CLK go to a Logic “1,” the gain code (A0, A1, A2,
B) signals are latched into the registers and held until both CS
and CLK return to “0.” Unused CS or CLK inputs should be tied
to ground . The CS and CLK inputs are functionally and electri-
cally equivalent.
OUT
FORCE
OUT
SENSE
V
OUT
0.1mF
–V
S
0.1mF
+V
S
+5V
A2
A1
A0
V
IN
TIMING SIGNAL
16 15 14 13 12 11 10 9
12345678
+
–
AD526
168421
GAIN NETWORK
A1 A0 CS CLK A2 B
LOGIC AND LATCHES
Figure 34. Latched Mode
