74LVT02
3.3 V Quad 2-input NOR gate
Rev. 3 — 7 April 2017 Product data sheet
1 General description
The 74LVT02 is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V.
The 74LVT02 is a quad 2-input NOR gate.
2 Features and benefits
Wide supply voltage range from 2.7 V to 3.6 V
Output capability: +64 mA and -32 mA
TTL input and output switching levels
Latch-up protection
JESD78 Class II exceeds 500 mA
Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to 85 °C
3 Ordering information
Table 1. Ordering information
PackageType
number
Temperature
range
Name Description Version
74LVT02D -40 °C to +85 °C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVT02DB -40 °C to +85 °C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LVT02PW -40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
Nexperia
74LVT02
3.3 V Quad 2-input NOR gate
74LVT02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 7 April 2017
2 / 13
4 Functional diagram
mna216
1A
1B
1Y
3
2
1
2A
2B
2Y
6
5
4
3A
3B
3Y
9
8
10
4A
4B
4Y
12
11
13
Figure 1. Logic symbol
001aah084
2
1
3
5
4
≥1
6
≥1
8
10
≥1
9
11
13
≥1
12
Figure 2. IEC logic symbol
mna215
A
B
Y
Figure 3. Logic diagram (one gate)
5 Pinning information
5.1 Pinning
74LVT02
1Y V
CC
1A 4Y
1B 4B
2Y 4A
2A 3Y
2B 3B
GND 3A
aaa-026557
1
2
3
4
5
6
7 8
10
9
12
11
14
13
Figure 4. Pin configuration for SOT108-1 (SO14)
74LVT02
1Y V
CC
1A 4Y
1B 4B
2Y 4A
2A 3Y
2B 3B
GND 3A
aaa-026558
1
2
3
4
5
6
7
8
10
9
12
11
14
13
Figure 5. Pin configuration for SOT337-1 and SOT402-1
(SSOP14 and TSSOP14)
5.2 Pin description
Table 2. Pin description
Symbol Pin Description
1Y to 4Y 1, 4, 10, 13 data output
1A to 4A 2, 5, 8, 11 data input
1B to 4B 3, 6, 9,12 data input
GND 7 ground (0 V)
V
CC
14 supply voltage
Nexperia
74LVT02
3.3 V Quad 2-input NOR gate
74LVT02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 7 April 2017
3 / 13
6 Functional description
Table 3. Function table
[1]
Input Output
nA nB nY
L L H
L H L
H L L
H H L
[1] H = HIGH voltage level; L = LOW voltage level
7 Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage -0.5 +4.6 V
V
I
input voltage
[1]
-0.5 +7.0 V
V
O
output voltage output in OFF-state or HIGH-state
[1]
-0.5 +7.0 V
I
IK
input clamping current V
I
< 0 V -50 - mA
I
OK
output clamping current V
O
< 0 V -50 - mA
output in LOW-state - 64 mAI
O
output current
output in HIGH-state -32 - mA
T
stg
storage temperature -65 +150 °C
T
j
junction temperature
[2]
- 150 °C
P
tot
total power dissipation T
amb
= -40 to +85 °C
[3]
- 500 mW
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which
are detrimental to reliability.
[3] For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
8 Recommended operating conditions
Table 5. Operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
CC
supply voltage 2.7 - 3.6 V
V
I
input voltage 0 - 5.5 V
I
OH
HIGH-level output current -20 - - mA
I
OL
LOW-level output current - - 32 mA
T
amb
ambient temperature in free-air -40 - +85 °C
Δt/ΔV input transition rise and fall rate outputs enabled - - 10 ns/V

74LVT02DB,118

Mfr. #:
Manufacturer:
Nexperia
Description:
Logic Gates 3.3V QUAD 2-INPUT
Lifecycle:
New from this manufacturer.
Delivery:
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