MC100EP016A
http://onsemi.com
8
APPLICATIONS INFORMATION
Cascading Multiple EP016A Devices
For applications which call for larger than 8‐bit counters
multiple EP016As can be tied together to achieve very wide
bit width counters. The active low terminal count (TC)
output and count enable input (CE) greatly facilitate the
cascading of EP016A devices. Two EP016As can be
cascaded without the need for external gating, however for
counters wider than 16 bits external OR gates are necessary
for cascade implementations.
Figure 4 below pictorially illustrates the cascading of 4
EP016As to build a 32‐bit high frequency counter. Note the
EP01 gates used to OR the terminal count outputs of the
lower order EP016As to control the counting operation of
the higher order bits. When the terminal count of the
preceding device (or devices) goes low (the counter reaches
an all 1s state) the more significant EP016A is set in its count
mode and will count one binary digit upon the next positive
clock transition. In addition, the preceding devices will also
count one bit thus sending their terminal count outputs back
to a high state disabling the count operation of the more
significant counters and placing them back into hold modes.
Therefore, for an EP016A in the chain to count, all of the
lower order terminal count outputs must be in the low state.
The bit width of the counter can be increased or decreased
by simply adding or subtracting EP016A devices from
Figure 4 and maintaining the logic pattern illustrated in the
same figure.
The maximum frequency of operation for a cascaded
counter chain is set by the propagation delay of the TC output,
the necessary setup time of the CE input, and the propagation
delay through the OR gate controlling it (for 16-bit counters
the limitation is only the TC propagation delay and the CE
setup time). Figure 4 shows EP01 gates used to control the
count enable inputs, however, if the frequency of operation is
slow enough, a LVECL OR gate can be used. Using the worst
case guarantees for these parameters.
Figure 4. 32‐Bit Cascaded EP016A Counter
CLK
P0 to P7
TC
CLK
P0 to P7
TC
CLK
EP01
P0 to P7 P0 to P7
MSB
EP016
Q0 to Q7Q0 to Q7 Q0 to Q7
EP016
Q0 to Q7
EP016
PECE
LSB
EP016
PECE
LOAD
LO
CLK CLK
CLK
EP01
TC
CLK
PECE
CLK
TC
CLK
PECE
CLK
Note that this assumes the trace delay between the TC
outputs and the CE inputs are negligible. If this is not the
case estimates of these delays need to be added to the
calculations.
Programmable Divider
The EP016A has been designed with a control pin which
makes it ideal for use as an 8‐bit programmable divider. The
TCLD pin (load on terminal count) when asserted reloads the
data present at the parallel input pin (Pn's) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 5
below illustrates the input conditions necessary for utilizing
the EP016A as a programmable divider set up to divide by
113.
