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ICE3BS03LJGXUMA1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
F3 PWM controller
ICE3BS03LJG
Functional Description
Version 2.0 10 6 Dec 2007
Figure 8 PWM Controlling
3.4 Startup Phase
Figure 9 Soft Start
In the Startup Phase, the IC provides a Soft Start
period to control the maximum primary current by
means of a duty cycle limitation. The Soft Start function
is a built-in function and it is controlled by an internal
counter.
Figure 10 Soft Start Phase
When the V
VCC
exceeds the on-threshold voltage, the
IC starts the Soft Start mode (see Figure 10).
The function is realized by an internal Soft Start
resistor, an current sink and a counter. And the
amplitude of the current sink is controlled by the
counter (see Figure 11).
Figure 11 Soft Start Circuit
After the IC is switched on, the V
SFOFTS
voltage is
controlled such that the voltage is increased step-
wisely (32 steps) with the increase of the counts. The
Soft Start counter would send a signal to the current
sink control in every 600us such that the current sink
X3.2
PWM OP
Improved
Current Mode
PWM Comparator
CS
Soft-Start Comparator
5V
C8
0.6V
FB
Optocoupler
R
FB
PWM-Latch
Soft-Start
Comparator
Soft Start
&
G7
C7
Gate Driver
0.6V
x3.2
PWM OP
CS
Soft S tart counter
Soft Start
Soft Start finish
SoftS
V
SoftS
V
SoftS2
V
SoftS1
5V
R
SoftS
Soft Start
Counter
I
2I
4I
SoftS
8I
32I
F3 PWM controller
ICE3BS03LJG
Functional Description
Version 2.0 11 6 Dec 2007
decrease gradually and the duty ratio of the gate drive
increases gradually. The Soft Start will be finished in
20ms (T
Soft-Start
) after the IC is switched on. At the end
of the Soft Start period, the current sink is switched off.
Figure 12 Gate drive signal under Soft-Start Phase
Within the soft start period, the duty cycle is increasing
from zero to maximum gradually (see Figure 12).
Figure 13 Start Up Phase
In addition to Start-Up, Soft-Start is also activated at
each restart attempt during Auto Restart.
The Start-Up time T
Start-Up
before the converter output
voltage V
OUT
is settled, must be shorter than the Soft-
Start Phase T
Soft-Start
(see Figure 13).
By means of Soft-Start there is an effective
minimization of current and voltage stresses on the
external power MOSFET, the clamp circuit and the
output overshoot and it helps to prevent saturation of
the transformer during Start-Up.
3.5 PWM Section
Figure 14 PWM Section Block
3.5.1 Oscillator
The oscillator generates a fixed frequency of 65KHz
with frequency jittering of ±4% (which is ±2.6KHz) at a
jittering period of 4ms.
A capacitor, a current source and a current sink which
determine the frequency are integrated. The charging
and discharging current of the implemented oscillator
capacitor are internally trimmed, in order to achieve a
very accurate switching frequency. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of D
max
=0.75.
Once the Soft Start period is over and when the IC goes
into normal operating mode, the switching frequency of
the clock is varied by the control signal from the Soft
t
V
SOFTS32
V
SoftS
Gate
Driver
t
T
Soft-Start
t
t
V
SoftS
t
V
SOFTS32
4.0V
T
Soft-Start
V
OUT
V
FB
V
OUT
T
Start-Up
Oscillator
Duty Cycle
max
Gate Driver
0.75
Clock
&
G9
1
G8
PWM Section
FF1
R
S
Q
Soft Start
Comparator
PWM
Comparator
Current
Limiting
Frequency
Jitter
Soft Start
Block
Gate
F3 PWM controller
ICE3BS03LJG
Functional Description
Version 2.0 12 6 Dec 2007
Start block. Then the switching frequency is varied in
range of 65KHz ± 2.6KHz at period of 4ms.
3.5.2 PWM-Latch FF
The output of the oscillator block provides continuous
pulse to the PWM-Latch which turns on/off the external
power MOSFET. After the PWM-Latch is set, it is reset
by the PWM comparator, the Soft Start comparator or
the Current -Limit comparator. When it is in reset mode,
the output of the gate driver is shut down immediately.
3.5.3 Gate Driver
Figure 15 Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the external power
MOSFET threshold. This is achieved by a slope control
of the rising edge at the gate driver’s output (see Figure
16).
Figure 16 Gate Rising Slope
Thus the leading switch on spike is minimized.
Furthermore the driver circuit is designed to eliminate
cross conduction of the output stage.
During power up, when VCC is below the undervoltage
lockout threshold V
VCCoff
, the output of the Gate Driver
is set to low in order to disable power transfer to the
secondary side.
3.6 Current Limiting
Figure 17 Current Limiting Block
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the external power MOSFET is
sensed via an external sense resistor R
Sense
. By means
of R
Sense
the source current is transformed to a sense
voltage V
Sense
which is fed into the pin CS. If the voltage
V
Sense
exceeds the internal threshold voltage V
csth,
the
comparator C10 immediately turns off the gate drive by
resetting the PWM Latch FF1.
A Propagation Delay Compensation is added to
support the immediate shut down of the external power
MOSFET with very short propagation delay. Thus the
influence of the AC input voltage on the maximum
output power can be reduced to minimal.
In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
VCC
1
PWM-Latch
Gate Driver
Gate
t
5V
ca. t = 130ns
C11
Current Limiting
C10
1.66V
C12
&
0.25V
Leading
Edge
Blanking
220ns
G10
Spike
Blanking
190ns
Over Power Protection
V
csth
Active Burst
Mode
PWM Latch
FF1
10k
D1
1pF
PWM-OP
CS
Latched Off
Mode
OPP
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

ICE3BS03LJGXUMA1

Mfr. #:
Buy ICE3BS03LJGXUMA1
Manufacturer:
Infineon Technologies
Description:
AC/DC Converters OFF-LINE SMPS CRRNT MODE CONTROLLER
Lifecycle:
New from this manufacturer.
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