CY62126EV30 MoBL
1-Mbit (64K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05486 Rev. *H Revised December 17, 2010
Features
■ High speed: 45 ns
■ Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive: –40 °C to +125 °C
■ Wide voltage range: 2.2 V to 3.6 V
■ Pin compatible with CY62126DV30
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 4 A
■ Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Offered in Pb-free 48-ball very fine pitch ball grid array (VFBGA)
and 44-pin thin small outline package (TSOP) II packages
Functional Description
The CY62126EV30 is a high performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life(MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE
HIGH). The input and
output pins (I/O
0
through I/O
15
) are placed in a high impedance
state when the device is deselected (CE
HIGH), the outputs are
disabled (OE
HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE
, BLE HIGH) or during a write
operation (CE
LOW and WE LOW).
To write to the device, take Chip Enable (CE
) and Write Enable
(WE
) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O
0
through I/O
7
) is written into the location
specified on the address pins (A
0
through A
15
). If Byte High
Enable (BHE
) is LOW, then data from I/O pins (I/O
8
through
I/O
15
) is written into the location specified on the address pins
(A
0
through A
15
).
To read from the device, take Chip Enable (CE
) and Output
Enable (OE
) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE
) is LOW, then data from the memory
location specified by the address pins appear on I/O
0
to I/O
7
. If
Byte High Enable (BHE
) is LOW, then data from memory
appears on I/O
8
to I/O
15
. See the “Truth Table” on page 11 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
64K x 16
RAM Array
I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
CE
WE
BHE
A
0
A
1
A
9
A
10
BLE
Logic Block Diagram
