Document #: 38-05486 Rev. *H Page 7 of 16
Switching Characteristics
Over the Operating Range
[11, 12]
Parameter Description
45 ns (Industrial) 55 ns (Automotive)
Unit
Min Max Min Max
Read Cycle
t
RC
Read cycle time 45 – 55 – ns
t
AA
Address to data valid – 45 – 55 ns
t
OHA
Data hold from address change 10 – 10 – ns
t
ACE
CE LOW to data valid
–
45
–
55 ns
t
DOE
OE LOW to data valid
–
22
–
25 ns
t
LZOE
OE LOW to Low Z
[13]
5
–
5
–
ns
t
HZOE
OE HIGH to High Z
[13, 14]
–
18
–
20 ns
t
LZCE
CE LOW to Low Z
[13]
10
–
10
–
ns
t
HZCE
CE HIGH to High Z
[13, 14]
–
18
–
20 ns
t
PU
CE LOW to power up 0
–
0
–
ns
t
PD
CE HIGH to power down
–
45
–
55 ns
t
DBE
BHE / BLE LOW to data valid
–
22
–
25 ns
t
LZBE
BHE / BLE LOW to Low Z
[13]
5
–
5
–
ns
t
HZBE
BHE / BLE HIGH to High Z
[13, 14]
–
18
–
20 ns
Write Cycle
[15]
t
WC
Write cycle time 45 – 55 – ns
t
SCE
CE LOW to write end 35
–
40
–
ns
t
AW
Address setup to write end 35 – 40 – ns
t
HA
Address hold from write end 0 – 0 – ns
t
SA
Address setup to write start 0 – 0 – ns
t
PWE
WE pulse width 35
–
40
–
ns
t
BW
BHE / BLE pulse width 35
–
40
–
ns
t
SD
Data setup to write end 25 – 25 – ns
t
HD
Data hold from write end 0 – 0 – ns
t
HZWE
WE LOW to High Z
[13, 14]
–
18
–
20 ns
t
LZWE
WE HIGH to Low Z
[13]
10
–
10
–
ns
Notes
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V
CC(typ)
/2, input pulse levels of 0 to V
CC(typ)
, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
12. AC timing parameters are subject to byte enable signals (BHE
or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
13. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
14. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
15. The internal write time of the memory is defined by the overlap of WE
, CE
= V
IL
, BHE, BLE or both = V
IL
. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
