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R5F21103FP#U0

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
R8C/10 Group 2. Central Processing Unit (CPU)
Rev.1.60 Jan 27, 2006 page 8 of 25
REJ03B0035-0160
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative address-
ing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0
can be combined with A0 to be used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch
between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.
2.8.2 Debug Flag (D)
The D flag is for debug only. Set to “0”.
2.8.3 Zero Flag (Z)
The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.
2.8.4 Sign Flag (S)
The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.
2.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag
is set to “1”.
2.8.6 Overflow Flag (O)
The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.
2.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The
I flag is set to “0” when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.
The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
When write to this bit, set to “0”. When read, its content is indeterminate.
R8C/10 Group 3. Memory
Rev.1.60 Jan 27, 2006 page 9 of 25
REJ03B0035-0160
3. Memory
Figure 3.1 is a memory map of this MCU. This MCU provides 1-Mbyte address space from addresses
0000016 to FFFFF16.
The internal ROM is allocated lower addresses beginning with address 0FFFF16. For example, a 16-
Kbyte internal ROM is allocated addresses from 0C00016 to 0FFFF16.
The fixed interrupt vector table is allocated addresses 0FFDC16 to 0FFFF16. They store the starting
address of each interrupt routine.
The internal RAM is allocated higher addresses beginning with address 0040016. For example, a 1-Kbyte
internal RAM is allocated addresses 0040016 to 007FF16. The internal RAM is used not only for storing
data, but for calling subroutines and stacks when interrupt request is acknowledged.
Special function registers (SFR) are allocated addresses 0000016 to 002FF16. The peripheral function
control registers are located them. All addresses, which have nothing allocated within the SFR, are re-
served area and cannot be accessed by users.
Figure 3.1 Memory Map
00000
16
0YYYY
16
0FFFF
16
002FF
16
00400
16
Internal ROM
SFR
(See Chapter 4 for details.)
0FFDC
16
0FFFF
16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer•Oscillation stop detection
Reset
(Reserved)
Type name
0XXXX
16
Internal RAM
FFFFF
16
Address 0XXXX
16
005FF
16
Internal RAM
Size
007FF
16
512 bytes
1K bytes
006FF
16
768 bytes
Address 0YYYY
16
0E000
16
Internal ROM
Size
0C000
16
8K bytes
16K bytes
0D000
16
12K bytes
Expansion area
(Reserved)
R5F21104FP, R5F21104DFP
R5F21103FP, R5F21103DFP
R5F21102FP, R5F21102DFP
NOTES :
1. Blank spaces are reserved. No access is allowed.
R8C/10 Group 4. Special Function Register (SFR)
Rev.1.60 Jan 27, 2006 page 10 of 25
REJ03B0035-0160
Watchdog timer start register WDTS XX
16
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C0
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0P
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0X
X
X
X0X
0
0
2
System clock control register 0 CM0 01101000
2
System clock control register 1 CM1 00100000
2
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D0
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2
INT0 input filter select register INT0F XXXXX000
2
0
0
0
01
6
0
0
0
11
6
0
0
0
21
6
0
0
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71
6
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81
6
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91
6
0
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A1
6
0
0
0
B1
6
0
0
0
C1
6
0
0
0
D1
6
0
0
0
E1
6
0
0
0
F1
6
0
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1
01
6
0
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1
11
6
0
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21
6
0
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31
6
0
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41
6
0
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51
6
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61
6
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71
6
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81
6
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91
6
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A1
6
0
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B1
6
0
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C1
6
0
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1
D1
6
0
0
1
E1
6
0
0
1
F1
6
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
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0
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X
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1R
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10
0
1
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0
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1
6
X
0
1
6
W
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RX
X
1
6
4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR
information
Table 4.1 SFR Information(1)
(1)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

R5F21103FP#U0

Mfr. #:
Buy R5F21103FP#U0
Manufacturer:
Renesas Electronics
Description:
16-bit Microcontrollers - MCU MCU 3/5V 12K Pb-Free 32-LQFP
Lifecycle:
New from this manufacturer.
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