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AT42QT1085 [DATASHEET]
9625D–AT42–05/2013
5. SPI Protocol for Object Protocol Memory Map Access
5.1 SPI Signals
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the host and the
QT1085. All communication with the device is carried out over the SPI. This is a synchronous serial data link that
operates in full-duplex mode. The host communicates with the QT1085 over the SPI using a master-slave
relationship, with the QT1085 acting in slave mode.
The SPI uses four logic signals:
Serial Clock (SCK) – output from the host.
Master Output, Slave Input (MOSI) – output from the host, input to the QT1085. Used by the host to send data
to the QT1085.
Master Input, Slave Output (MISO) – input to the host, output from the QT1085. Used by the QT1085 to send
data to the host.
Slave Select (SS) – active low output from the host.
The SPI signals operate in the following way:
SCK Idles high.
MISO and MOSI are set up on falling edges, read on rising edges.
SS must be held low throughout the exchange. SS must be pulled high for at least 2 ms after a Read or 10 ms
after a Write before another exchange can be initiated.
Figure 5-1. SPI Signals
5.2 Communications Protocol
5.2.1 MOSI Data
A 3-byte command sequence is transmitted by the host on MOSI, setting the memory map address pointer, a Read /
Write indication, and the number of bytes which will be read or written.
Read / Write direction is set in Byte 0 Bit 0, where '0' = Write, '1' = Read.
Memory map is addressed in 15 bits, where the lower 7 bits are transmitted at Byte 0, Bits 6 – 1 and the upper 8 bits
at Byte 1.
SAMPLE
MOSI/MISO
CHANGE
MOSI PIN
CHANGE
MISO PIN
SCK
SS
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
