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74HC132DR2G

P1-P3P4-P6P7-P9
74HC132
http://onsemi.com
4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol Parameter Test Conditions (V)
*55_C to 25_C 85_C 125_C
Unit
V
T+
max Maximum Positive−Going
Input Threshold Voltage
(Figure 5)
V
OUT
= 0.1 V
|I
OUT
| 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
T+
min Minimum Positive−Going
Input Threshold Voltage
(Figure 5)
V
OUT
= 0.1 V
|I
OUT
| 20 mA
2.0
4.5
6.0
1.0
2.3
3.0
0.95
2.25
2.95
0.95
2.25
2.95
V
V
T–
max Maximum Negative−Going
Input Threshold Voltage
(Figure 5)
V
OUT
= V
CC
– 0.1 V
|I
OUT
| 20 mA
2.0
4.5
6.0
0.9
2.0
2.6
0.95
2.05
2.65
0.95
2.05
2.65
V
V
T–
min Minimum Negative−Going
Input Threshold Voltage
(Figure 5)
V
OUT
= V
CC
– 0.1 V
|I
OUT
| 20 mA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
H
max
(Note 7)
Maximum Hysteresis
Voltage
(Figure 5)
V
OUT
= 0.1 V or V
CC
– 0.1 V
|I
OUT
| 20 mA
2.0
4.5
6.0
1.2
2.25
3.0
1.2
2.25
3.0
1.2
2.25
3.0
V
V
H
min
(Note 7)
Minimum Hysteresis
Voltage
(Figure 5)
V
OUT
= 0.1 V or V
CC
– 0.1 V
|I
OUT
| 20 mA
2.0
4.5
6.0
0.2
0.4
0.5
0.2
0.4
0.5
0.2
0.4
0.5
V
V
OH
Minimum High−Level
Output Voltage
V
IN
V
T−
min or V
T+
max
|I
OUT
| 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN
−V
T−
min or V
T+
max
|I
OUT
| 4.0 mA
|I
OUT
| 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low−Level
Output Voltage
V
IN
≥ V
T+
max
|I
OUT
| 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
≥ V
T+
max |I
OUT
| 4.0 mA
|I
OUT
| 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
IN
Maximum Input Leakage
Current
V
IN
= V
CC
or GND 6.0 0.1 1.0 1.0
mA
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
= V
CC
or GND
I
OUT
= 0 mA
6.0 2.0 20 40
mA
7. V
H
min (V
T+
min) (V
T−
max); V
H
max = (V
T+
max) (V
T−
min).
8. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
74HC132
http://onsemi.com
5
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
V
CC
Guaranteed Limit
Symbol Parameter (V)
*55_C to 25_C 85_C 125_C
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 3 and 4)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 3 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
in
Maximum Input Capacitance — 10 10 10 pF
9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (per Gate) (Note 10) 24 pF
10.Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
. For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Figure 3. Switching Waveforms
t
r
V
CC
GND
90%
50%
10%
90%
50%
10%
INPUT
A OR B
Y
t
PHL
t
PLH
t
THL
t
TLH
*Includes all probe and jig capacitance
Figure 4. Test Circuit
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
t
f
74HC132
http://onsemi.com
6
Figure 5. Typical Input Threshold, V
T+
, V
T−
Versus Power Supply Voltage
Figure 6. Typical Schmitt−Trigger Applications
4
3
2
1
23456
V
CC
, POWER SUPPLY VOLTAGE (VOLTS)
V
H
typ
V
H
typ = (V
T+
typ) − (V
T−
typ)
(a)A SCHMITT TRIGGER SQUARES UP INPUTS
(a)WITH SLOW RISE AND FALL TIMES
(b)A SCHMITT TRIGGER OFFERS MAXIMUM
NOISE IMMUNITY
V
IN
V
OUT
V
H
V
CC
V
T+
V
T−
GND
V
OH
V
OL
V
IN
V
H
V
OUT
V
CC
V
T+
V
T−
GND
V
OH
V
OL
V
CC
V
IN
V
OUT
V
T
, TYPICAL INPUT THRESHOLD VOLTAGE
(VOLTS)
P1-P3P4-P6P7-P9

74HC132DR2G

Mfr. #:
Buy 74HC132DR2G
Manufacturer:
ON Semiconductor
Description:
Logic Gates QUAD 2 INPUT NAND GATE
Lifecycle:
New from this manufacturer.
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