AD9550BCPZ-REEL7 Datasheet AD9550BCPZ, AD9550BCPZ-REEL7 | P4-P6

AD9550

Rev. 0 | Page 3 of 20

SPECIFICATIONS

Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)

values apply for VDD = 3.3 V; T

= 25°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLY VOLTAGE 3.135 3.30 3.465 V Pin 18, Pin 21, and Pin 28

POWER CONSUMPTION Tested with both output channels active at maximum

output frequency; LVPECL and LVDS outputs use a 100 Ω

termination between both pins of the output driver

Total Current 162 185 mA

VDD Current By Pin

Pin 18 93 106 mA

Pin 21

LVDS Configured Output 35 41 mA

LVPECL Configured Output 36 42 mA

CMOS Configured Output 29 34 mA

Pin 28

LVDS Configured Output 35 41 mA

LVPECL Configured Output 36 42 mA

CMOS Configured Output 29 34 mA

LOGIC INPUT PINS

Input Characteristics

Logic 1 Voltage, V

1.02 V For the CMOS inputs, a static Logic 1 results from either

a pull-up resistor or no connection

Logic 0 Voltage, V

0.64 V

Logic 1 Current, I

3 µA

Logic 0 Current, I

17 µA

LOGIC OUTPUT PINS

Output Characteristics Tested at 1 mA load current

Output Voltage High, V

2.7 V

Output Voltage Low, V

0.19 V

RESET

Input Characteristics

Input Voltage High, V

1.96 V

Input Voltage Low, V

0.85 V

Input Current High, I

INH

0.3 12.5 µA

Input Current Low, I

INL

31 43 µA

Minimum Pulse Width Low 150 µs Tested with an active source driving the

RESET

REFERENCE CLOCK INPUT CHARACTERISTICS

CMOS Single-Ended Input

Input Frequency Range 0.008 200 MHz

Input High Voltage 1.62 V

Input Low Voltage 0.52 V

Input Threshold Voltage 1.0 V When ac coupling to the input receiver, the user must

dc bias the input to 1 V

Input High Current 0.04 µA

Input Low Current 0.03 µA

Input Capacitance 3 pF

Duty Cycle Pulse width high and pulse width low establish the

bounds for duty cycle

Pulse Width Low 2 ns

Pulse Width High 2 ns

AD9550

Rev. 0 | Page 4 of 20

Parameter Min Typ Max Unit Test Conditions/Comments

×2 Frequency Multiplier 125 MHz To avoid excessive reference spurs, the ×2 multiplier

requires 48% to 52% duty cycle; reference clock input

frequencies greater than 125 MHz require the use of

the divide-by-5 prescaler

VCO CHARACTERISTICS

Frequency Range 3350 4050 MHz

VCO Gain 45 MHz/V

VCO Tracking Range ±300 ppm

PLL Lock Time Using the pin selected frequency settings; lock time is

from the rising edge of the

RESET

pin to the rising

edge of the LOCKED pin

Low Bandwidth Setting (170 Hz) Applies for Pin A3 to Pin A0 = 0001 to 1100, or for Pin A3

to Pin A0 = 1111

13.3 kHz PFD Frequency 214 ms

16 kHz PFD Frequency 176 ms

Medium Bandwidth Setting (20 kHz) Applies for Pin A3 to Pin A0 = 1110 and Pin Y5 to Pin Y0=

111111

1.5625 MHz PFD Frequency 2 ms

High Bandwidth Setting (75 kHz) Applies for Pin A3 to Pin A0 = 1101 to 1110

2.64 MHz PFD Frequency 1.50 ms

4.86 MHz PFD Frequency 0.89 ms

The A3 to A0 and Y5 to Y0 pins have 100 kΩ internal pull-up resistors. The OM2 to OM0 pins have 40 kΩ pull-up resistors.

The

RESET

pin has a 100 kΩ internal pull-up resistor.

OUTPUT CHARACTERISTICS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL MODE

Differential Output Voltage Swing 690 800 890 mV Output driver static (for dynamic performance see

Figure 15)

Common-Mode Output Voltage VDD − 1.66 VDD − 1.34 VDD − 1.01 V Output driver static

Frequency Range 0 810 MHz

Duty Cycle 40 60 % Up to 805 MHz output frequency

Rise/Fall Time

(20% to 80%) 255 305 ps 100 Ω termination between both pins of the output driver

LVDS MODE

Differential Output Voltage Swing Output driver static (for dynamic performance see

Figure 15)

Balanced, V

297 398 mV Voltage swing between output pins; output driver static

Unbalanced, ΔV

8.3 mV Absolute difference between voltage swing of normal

pin and inverted pin; output driver static

Offset Voltage

Common Mode, V

1.17 1.35 V Output driver static

Common-Mode Difference, ΔV

7.3 mV Voltage difference between output pins; output driver

static

Short-Circuit Output Current 17 24 mA

Frequency Range 0 810 MHz

Duty Cycle 40 60 % Up to 805 MHz output frequency

Rise/Fall Time

(20% to 80%) 285 355 ps 100 Ω termination between both pins of the output

driver

AD9550

Rev. 0 | Page 5 of 20

Parameter Min Typ Max Unit Test Conditions/Comments

CMOS MODE

Output Voltage High, V

Output driver static

= 10 mA 2.8 V

= 1 mA 2.8 V

Output Voltage Low, V

Output driver static

= 10 mA 0.5 V

= 1 mA 0.3 V

Frequency Range 0 200 MHz 3.3 V CMOS; output toggle rates in excess of the

maximum are possible, but with reduced amplitude

(see Figure 14)

Duty Cycle 45 55 % At maximum output frequency

Rise/Fall Time

(20% to 80%) 500 745 ps 3.3 V CMOS; 10 pF load

The listed values are for the slower edge (rise or fall).

JITTER CHARACTERISTICS

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

JITTER GENERATION

Output

12 kHz to 20 MHz

LVPECL 1.31 ps rms Input = 122.88 MHz, output = 155.52 MHz

1.28 ps rms Input = 19.44 MHz, output = 245.76 MHz

0.89 ps rms Input = 25 MHz, output = 125 MHz, Pin A3 to Pin A0 = 1110, Pin Y5

to Pin Y0 = 111111 (see Figure 3)

LVDS Output 1.32 ps rms Input = 122.88 MHz, output = 155.52 MHz

1.29 ps rms Input = 19.44 MHz, output = 245.76 MHz

CMOS Output 1.24 ps rms Input = 122.88 MHz, output = 155.52 MHz

1.26 ps rms Input = 19.44 MHz, output = 245.76 MHz, see Figure 14 regarding

CMOS toggle rates above 250 MHz

50 kHz to 80 MHz Input = 122.88 MHz, output = 155.52 MHz

LVPECL 0.44 ps rms Input = 122.88 MHz, output = 155.52 MHz

0.75 ps rms Input = 19.44 MHz, output = 245.76 MHz

0.58 ps rms Input = 25 MHz, output = 125 MHz, Pin A3 to Pin A0 = 1110, Pin Y5

to Pin Y0 = 111111 (see Figure 3)

LVDS 0.45 ps rms Input = 122.88 MHz, output = 155.52 MHz

0.76 ps rms Input = 19.44 MHz, output = 245.76 MHz

CMOS 0.39 ps rms Input = 122.88 MHz, output = 155.52 MHz

0.44 ps rms Input = 19.44 MHz, output = 245.76 MHz, see Figure 14 regarding

CMOS toggle rates above 250 MHz

JITTER TRANSFER BANDWIDTH See the Typical Performance Characteristics section

Bandwidth Setting

Low 170 Hz

Medium 20 kHz

High 75 kHz

JITTER TRANSFER PEAKING See the Typical Performance Characteristics section

Bandwidth Setting

Low 1.3 dB

Medium 0 dB

High 0.08 dB

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD9550BCPZ-REEL7

Mfr. #:

Buy AD9550BCPZ-REEL7

Manufacturer:

Analog Devices Inc.

Description:

Clock Generators & Support Products Integer-N Clock Translator

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD9550BCPZ-REEL7

AD9550BCPZ-REEL7

Products related to this Datasheet