AD9550
Rev. 0 | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage (VDD) 3.6 V
Maximum Digital Input Voltage −0.5 V to VDD + 0.5 V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD9550
Rev. 0 | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. NC = NO CONNECT.
2. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
PIN 1
INDICATOR
1Y4
2Y5
3A0
4A1
5A2
6A3
7REF
8GND
24 GND
23 OUT2
22
21 VDD
20 LOCKED
19 LDO
18 VDD
17 LDO
9
NC
10
NC
11
GND
12
13
OM1
14
OM0
15
RESET
16
FILTER
32
Y3
31
Y
2
30
Y1
29
Y
0
28
VDD
27
OUT1
26
25
GND
TOP VIEW
(Not to Scale)
AD9550
OUT1
OUT2
OM2
9057-002
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
29, 30, 31,
32, 1, 2
Y0, Y1, Y2, Y3,
Y4, Y5
I
Control Pins. These pins select one of 52 preset output frequency combinations for OUT1 and
OUT2. Each pin has an internal 100 kΩ pull-up resistor.
3, 4, 5, 6 A0, A1, A2, A3 I
Control Pins. These pins select one of 15 preset input reference frequencies. Each pin has an
internal 100 kΩ pull-up resistor.
7 REF I Reference Clock Input. Connect this pin to a single-ended active clock input signal.
8, 11, 24, 25 GND P Ground.
9, 10 NC No Connection. Make no external connection to these pins. Do not connect to GND or VDD.
12, 13, 14
OM2, OM1,
OM0
I
Control Pins. These pins select one of eight preset output configurations (see Table 10). Each pin
has an internal 40 kΩ pull-up resistor.
15
RESET
I
Reset Internal Logic. This is a digital input pin. This pin is active low with a 100 kΩ internal pull-up
resistor and resets the internal logic to default states (see the Automatic Power-On Reset section).
16 FILTER I/O
Loop Filter Node for the PLL. Connect external loop filter components (see Figure 24) from this pin
to Pin 17 (LDO).
17, 19 LDO P/O LDO Decoupling Pins. Connect a 0.47 μF decoupling capacitor from each of these pins to ground.
18, 21, 28 VDD P
Power Supply Connection: 3.3 V Supply. Pin 21 supplies the OUT2 driver and Pin 28 supplies the
OUT1 driver.
20 LOCKED O Locked Status Indicator for the PLL. Active high.
26, 22
OUT1
, OUT2
O Complementary Square Wave Clocking Outputs.
27, 23 OUT1, OUT2 O Square Wave Clocking Outputs.
N/A
2
EP Exposed Die Pad. The exposed die pad must be connected to GND.
1
I is input, I/O is input/output, O is output, P is power, and P/O is power/output.
2
N/A means not applicable.
AD9550
Rev. 0 | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
10 100 1k 10k 100k 1M 10M 100M
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
JITTER BANDWIDTH
12kHz TO 20MHz
50kHz TO 80MHz
JITTER (rms)
0.89ps
0.58ps
09057-103
Figure 3. Phase Noise (f
REF
= 25 MHz, f
OUT1
= 125 MHz)
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
10 100 1k 10k 100k 1M 10M 100M
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
JITTER BANDWIDTH
12kHz TO 20MHz
50kHz TO 80MHz
JITTER (rms)
1.32ps
0.41ps
09057-023
Figure 4. Phase Noise (f
REF
= 25 MHz, f
OUT1
= 156.25 MHz)
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
10 100 1k 10k 100k 1M 10M 100M
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
JITTER BANDWIDTH
12kHz TO 20MHz
50kHz TO 80MHz
JITTER (rms)
1.25ps
0.63ps
09057-004
Figure 5. Phase Noise (f
REF
= 61.44 MHz, f
OUT1
= 122.88 MHz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
100 1k
10k 100k 1M 10M 100M
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
JITTER BANDWIDTH
12kHz TO 20MHz
50kHz TO 80MHz
JITTER (rms)
0.73ps
0.51ps
09057-005
Figure 6. Phase Noise (f
REF
= 77.76 MHz, f
OUT1
= 622.08 MHz)
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
10 100 1k 10k 100k
1M 10M 100M
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
JITTER BANDWIDTH
12kHz TO 20MHz
50kHz TO 80MHz
JITTER (rms)
1.26ps
0.49ps
09057-006
Figure 7. Phase Noise (f
REF
= 19.44 MHz, f
OUT1
= 155.52 MHz)
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
10 100 1k 10k 100k
1M 10M 100M
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
JITTER BANDWIDTH
12kHz TO 20MHz
50kHz TO 80MHz
JITTER (rms)
1.27ps
0.54ps
09057-007
Figure 8. Phase Noise (f
REF
= 8 kHz, f
OUT1
= 155.52 MHz)

AD9550BCPZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Clock Generators & Support Products Integer-N Clock Translator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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