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SL23EP09NZSC-1H

P1-P3P4-P6P7-P9P10-P12
Rev 2.2, May 6, 2008 Page 7 of 11
SL23EP09NZ
Switching Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Symbol
Condition
Min
Typ
Max
Unit
Output Frequency Range
FOUT1
CL=15pf
0
–
180
MHz
FOUT2
CL=30pf
0
–
80
MHz
Input Duty Cycle
DC1
Measured at VDD/2
20
50
80
%
Output Duty Cycle
DC2
CL=15pF, Fout=166MHz
Measured at VDD/2
45
50
55
%
Output Duty Cycle
DC3
CL=30pF, Fout=80MHz
Measured at VDD/2
40
50
60
%
Output Rise/Fall Time
tr/f-1
Measured at 0.6V to 1.8V
CL=15pF
–
–
1.6
ns
Output Rise/Fall Time
tr/f-2
Measured at 0.6V to 1.8V
CL=30pF
–
–
2.0
ns
Output Skew
SKW1
Measured at VDD/2 and
Outputs are equally loaded
–
90
180
ps
Part to Part Skew
SKW2
Measured at VDD/2 and
Outputs are equally loaded
–
120
240
ps
Propagation Delay Time
PDT
Measured at VDD/2 from CLKIN to
Output Clock rising edge and Outputs
are equally loaded
3.0
4.0
5.0
ns
Cycle-to-Cycle Jitter
CCJ1
CLKIN=66MHz and CL=0 (No Load)
–
50
100
ps
Cycle-to-Cycle Jitter
CCJ2
CLKIN=166MHz and CL=0 (No Load)
–
35
70
ps
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
Description
Symbol
Condition
Min
Typ
Max
Unit
Input LOW Voltage
VINL
CLKIN
–
–
0.7
V
Input HIGH Voltage
VINH
CLKIN
1.7
–
VDD+0.3
V
Input LOW Current
IINL
0 < VIN < 0.8V
–
–
15
µA
Input HIGH Current
IINH
2.4V < VIN < VDD
–
–
25
µA
Output Low Voltage
VOL
IOL=8mA
–
–
0.4
V
Output High Voltage
VOH
IOH=-8mA
VDD-0.6
–
–
V
Power Supply Current
IDD1
CLKIN=33.3MHz, CL=0
–
10
14
mA
Power Supply Current
IDD2
CLKIN=66.6MHz, CL=0
–
12
17
mA
Power Supply Current
IDD3
CLKIN=133.3MHz, CL=0
–
16
23
mA
Not Recommended
for New Designs
Rev 2.2, May 6, 2008 Page 8 of 11
SL23EP09NZ
Switching Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
Description
Symbol
Condition
Min
Typ
Max
Unit
Output Frequency Range
FOUT1
CL=15pf
0
–
180
MHz
FOUT2
CL=30pf
0
–
80
MHz
Input Duty Cycle
DC1
Measured at VDD/2
20
50
80
%
Output Duty Cycle
DC2
CL=15pF, Fout=166MHz
Measured at VDD/2
45
50
55
%
Output Duty Cycle
DC3
CL=30pF, Fout=100MHz
Measured at VDD/2
40
50
60
%
Output Rise/Fall Time
tr/f-1
Measured at 0.8V to 2.0V
CL=15pF
–
–
1.8
ns
Output Rise/Fall Time
tr/f-2
Measured at 0.8V to 2.0V
CL=30pF
–
–
2.2
ns
Output Skew
SKW1
Measured at VDD/2 and
Outputs are equally loaded
–
100
200
ps
Part to Part Skew
SKW2
Measured at VDD/2 and
Outputs are equally loaded
–
140
280
ps
Propagation Delay Time
PDT
Measured at VDD/2 from CLKIN to
Output Clock rising edge and Outputs
are equally loaded
2.5
4.0
5.5
ns
Cycle-to-Cycle Jitter
CCJ1
CLKIN=66MHz and CL=0 (No Load)
–
60
120
ps
Cycle-to-Cycle Jitter
CCJ2
CLKIN=133MHz and CL=0 (No Load)
–
50
100
ps
Not Recommended
for New Designs
Rev 2.2, May 6, 2008 Page 9 of 11
SL23EP09NZ
External Components & Design Considerations
Typical Application Schematic
SL23EP09NZ
0.1μF
BUF_IN
OUTPUT2
GND
VDD
1
4,8,13
5,9,12
16
3
2
CL
OUTPUT1
CL
CL
OUTPUT9
Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1μF must be used between all VDD and VSS pins. Place the
capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and
to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD
pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output
clocks and the load is over 1 ½ inch. Place the series termination resistors as close to the clock outputs as possible.
Not Recommended
for New Designs
P1-P3P4-P6P7-P9P10-P12

SL23EP09NZSC-1H

Mfr. #:
Buy SL23EP09NZSC-1H
Manufacturer:
Silicon Labs
Description:
Clock Buffer 0 to 220MHz, 9 Outputs Fanout Buffer (NZDB), 3.3V to 2.5V High Drive
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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