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MC13201FCR2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
MC13201 Technical Data, Rev. 1.3,
Freescale Semiconductor 13
6.2.2 SPI Transaction Operation
Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13201 requires that a complete
SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion
of CE
to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the
transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and
identifies the access as being a read or write operation. In this context, a write is data written to the
MC13201 and a read is data written to the SPI master. The following SPI bursts will be either the write
data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).
Although the SPI bus is capable of sending data simultaneously between master and slave, the MC13201
never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to
a larger number depending on the type of access. The number of payload bytes sent will always be an even
integer. After the final SPI burst, CE
is negated to high to signal the end of the transaction. Refer to the
MC13201 Reference Manual, (MC13201RM) for more details on SPI registers and transaction types.
An example SPI read transaction with a 2-byte payload is shown in Figure 9.
Figure 9. SPI Read Transaction Diagram
CE
SPICLK
MISO
MOSI
Valid
Valid Valid
Clock Burst
Header Read data
MC13201 Technical Data, Rev. 1.3,
14 Freescale Semiconductor
7 Pin Connections
Table 8. Pin Function Description
Pin # Pin Name Type Description Functionality
1 RFIN_M RF Input RF input/output negative. When used with internal T/R switch, this is
a bi-directional RF port for the internal LNA
and PA
2 RFIN_P RF Input RF input/output positive. When used with internal T/R switch, this is
a bi-directional RF port for the internal LNA
and PA
3 CT_Bias Control voltage Bias voltage/control signal for external
RF components
When used with internal T/R switch,
provides RX ground reference and TX
VDDA reference for use with external
balun. Can also be used as a control signal
for external LNA, PA, or T/R switch.
4 NC Tie to Ground.
5 PAO_P RF Output /DC Input RF Power Amplifier Output Positive. Open drain. Connect to VDDA through a
bias network when used with an external
balun. Not used when internal T/R switch is
used.
6 PAO_M RF Output/DC Input RF Power Amplifier Output Negative. Open drain. Connect to VDDA through a
bias network when used with an external
balun. Not used when internal T/R switch is
used.
7 SM Input Test mode pin. Must be grounded for normal operation.
8 GPIO4
1
Digital Input/ Output General Purpose Input/Output 4. See Footnote 1.
9 GPIO3
1
Digital Input/ Output General Purpose Input/Output 3. See Footnote 1.
10 GPIO2
1
Digital Input/ Output General Purpose Input/Output 2.
When gpio_alt_en, Register 9, Bit 7 =
1, GPIO2 functions as a “CRC Valid”
indicator.
See Footnote 1.
11 GPIO1
1
Digital Input/ Output General Purpose Input/Output 1.
When gpio_alt_en, Register 9, Bit 7 =
1, GPIO1 functions as an “Out of Idle”
indicator.
See Footnote 1.
12 RST Digital Input Active Low Reset. While held low, the
IC is in Off Mode and all internal
information is lost from RAM and SPI
registers. When high, IC goes to IDLE
Mode, with SPI in default state.
MC13201 Technical Data, Rev. 1.3,
Freescale Semiconductor 15
13 RXTXEN
2
Digital Input Active High. Low to high transition
initiates RX or TX sequence
depending on SPI setting. Should be
taken high after SPI programming to
start RX or TX sequence and should
be held high through the sequence.
After sequence is complete, return
RXTXEN to low. When held low,
forces Idle Mode.
See Footnote 2
14 ATTN
2
Digital Input Active Low Attention. Transitions IC
from either Hibernate or Doze Modes
to Idle.
See Footnote 2
15 CLKO Digital Output Clock output to host MCU.
Programmable frequencies of:
16 MHz, 8 MHz, 4 MHz, 2 MHz, 1
MHz, 62.5 kHz, 32.786+ kHz
(default),
and 16.393+ kHz.
16 SPICLK
2
Digital Clock Input External clock input for the SPI
interface.
See Footnote 2
17 MOSI
2
Digital Input Master Out/Slave In. Dedicated SPI
data input.
See Footnote 2
18 MISO
3
Digital Output Master In/Slave Out. Dedicated SPI
data output.
See Footnote 3
19 CE
2
Digital Input Active Low Chip Enable. Enables SPI
transfers.
See Footnote 2
20 IRQ Digital Output Active Low Interrupt Request. Open drain device.
Programmable 40 kΩ internal pull-up.
Interrupt can be serviced every 6 µs with
<20 pF load.
Optional external pull-up must be >4 k
Ω.
21 VDDD Power Output Digital regulated supply bypass. Decouple to ground.
22 VDDINT Power Input Digital interface supply & digital
regulator input. Connect to Battery.
2.0 to 3.4 V. Decouple to ground.
23 GPIO5
1
Digital Input/Output General Purpose Input/Output 5. See Footnote 1
24 GPIO6
1
Digital Input/Output General Purpose Input/Output 6. See Footnote 1
25 GPIO7
1
Digital Input/Output General Purpose Input/Output 7. See Footnote 1
26 XTAL1 Input Crystal Reference oscillator input. Connect to 16 MHz crystal and load
capacitor.
Table 8. Pin Function Description (continued)
Pin # Pin Name Type Description Functionality
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

MC13201FCR2

Mfr. #:
Buy MC13201FCR2
Manufacturer:
NXP / Freescale
Description:
RF Transceiver TORO IC NON 802.15.4
Lifecycle:
New from this manufacturer.
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