MC13201 Technical Data, Rev. 1.3,
4 Freescale Semiconductor
3 Block Diagrams
Figure 1 shows a simplified block diagram of the MC13201 which is an 802.15.4 Standard compatible
transceiver that provides the functions required in the physical layer (PHY) specification.
Figure 1. 802.15.4 modem Simplified Block Diagram
Figure 2 shows the basic system block diagram for the MC13201 in an application. Interface with the
transceiver is accomplished through a 4-wire SPI port and interrupt request line. The media access control
(MAC), drivers, and network and application software (as required) reside on the host processor. The host
can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on application
requirements.
Figure 2. System Level Block Diagram
Phase Shift Modulator
RST
GPIO1
GPIO2
GPIO3
GPIO4
XTAL2
XTAL1
RFIN_M
(PAO_M)
PAO_P
PAO_M
MOSI
MISO
SPICLK
RXTXEN
CE
ATTN
GPIO5
GPIO6
GPIO7
Receive
Packet RAM
Transmit
Packet RAM 1
Transmit RAM
Arbiter
Receive RAM
Arbiter
PA
VCO
Crystal
Oscillator
Sy mbol
Generation
FCS
Generation
Header
Generation
MUX
Sequence
Manager
(Control Logic)
VDDLO2 ÷4
256 MHz
2.45 GHz
LNA
1st IF M ix er
IF = 65 MHz
2nd IF Mixer
IF = 1 M Hz
PMA
Decimation
Filter
Matched
Filter
Baseband
Mixer
DCD
Correlator
Symbol
Synch & Det
CCA
Packet
Processor
IR Q
Arbiter
24 Bit Ev ent Timer
IR Q
16 MHz
AGC
Analog
Regulator VBATT
Digital
Regulator L
Digital
Regulator H
Pow er-Up
Control
Logic
Crystal
Regulator
VCO
Regulator
VDDINT
Programmable
Prescaler
CLKO
4 Programmable
Timer Comparators
Synthesizer
VDDD
VDDVCO
SERIAL
PERIPHERAL
INTERFACE
(SPI)
VDDA
VDDLO1
Transmit
Packet RAM 2
T / R
RFIN_P
(PAO_P)
CT_Bias
Analog Receiver
MC13201
Frequency
Generation
Analog
Transmitter
Voltage
Regulators
Power Up
Management
Control
Logic
Buffer RAM
Digital Transceiver
SPI
and GPIO
Microcontroller
SPI
ROM
(Flash)
RAM
CPU A/D
Timer
Application
IRQ Arbiter
RAM Arbiter
Timer
Network
MAC
PHY Driver
MC13201 Technical Data, Rev. 1.3,
Freescale Semiconductor 5
4 Data Transfer Mode
The MC13201 has a data transfer mode called Packet Mode where data is buffered in on-chip Packet
RAMs. There is a TX Packet RAM and an RX Packet RAM, each of which are 64 locations by 16 bits
wide.
4.1 Packet Structure
Figure 3 shows the packet structure of the MC13201 which is consistent with the 802.15.4 Standard.
Payloads of up to 125 bytes are supported. The MC13201 adds a four-byte preamble, a one-byte Start of
Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A Frame Check
Sequence (FCS) is calculated and appended to the end of the data.
Figure 3. MC13201 Packet Structure
4.2 Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon
the baseband energy integrated over a specific time interval. The digital backend performs Differential
Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset
QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.
The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in
RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the
transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured
over a 64 µs period after the packet preamble and stored in RAM.
The MC13201 uses a packet mode where the data is processed as an entire packet and stored in Rx Packet
RAM. The MCU is notified that an entire packet has been received via an interrupt.
Figure 4 shows CCA reported power level versus input power. Note that CCA reported power saturates at
about -57 dBm input power which is well above 802.15.4 Standard requirements. Figure 5 shows energy
detection/LQI reported level versus input power.
NOTE
For both graphs, the required 802.15.4 Standard accuracy and range limits
are shown. A 3.5 dBm offset has been programmed into the CCA reporting
level to center the level over temperature in the graphs.
Preamble SFD FLI Payload Data FCS
4 bytes 1 byte 1 byte 125 bytes maximum 2 bytes
MC13201 Technical Data, Rev. 1.3,
6 Freescale Semiconductor
Figure 4. Reported Power Level versus Input Power in CCA Mode
Figure 5. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator
4.3 Transmit Path Description
For the transmit path, the TX data that was previously stored in TX Packet RAM is retrieved, formed into
packets per the 802.15.4 PHY, spread, and then up-converted to the transmit frequency.
Because the MC13201 is used in packet mode, data is processed as an entire packet. The data is first loaded
into the TX buffer. The MCU then requests that the MC13201 transmit the data. The MCU is notified via
an interrupt when the whole packet has successfully been transmitted.
-100
-90
-80
-70
-60
-50
-90 -80 -70 -60 -50
Input Power (dBm)
802.15.4 Accuracy
and range Requirements
-85
-75
-65
-55
-45
-35
-25
-15
-85 -75 -65 -55 -45 -35 -25 -15
Input Power Level (dBm)
Reported Power Level (dBm)
802.15.4 Accuracy
and Range Requirements

MC13201FCR2

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
RF Transceiver TORO IC NON 802.15.4
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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