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EL9115ILZ

P1-P3P4-P6P7-P9P10-P10
4
FN7441.7
January 12, 2012
17 TESTB Blue channel phase detector output
18 TESTG Green channel phase detector output
19 TESTR Red channel phase detector output
20 X2 Sets gain to 2X if input high; X1 otherwise
Thermal Pad Must be connected to -5V
Pin Descriptions (Continued)
PIN NUMBER PIN NAME PIN DESCRIPTION
Typical Performance Curves
FIGURE 1. GAIN vs FREQUENCY FIGURE 2. GAIN vs FREQUENCY
FIGURE 3. DC OFFSET vs DELAY TIME (GAIN = 2X) FIGURE 4. DC OFFSET vs DELAY TIME (GAIN = 1X)
Delay 10, 20, 30, 40 and 50ns
Delay = 62ns
-3dB@80MHz
Delay = 0ns
-3dB@122MHz
Delay = 62ns
Delay 10, 20, 30, 40 and 50ns
Delay = 0ns
-140
-120
-100
-80
-60
-40
-20
0
20
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
PROGRAMMED DELAY (ns)
DC OFFSET (mV)
-70
-60
-50
-40
-30
-20
-10
0
10
20
0 10203040506070
PROGRAMMED DELAY (ns)
DC OFFSET (mV)
EL9115
5
FN7441.7
January 12, 2012
FIGURE 5. RISE TIME vs DELAY TIME
FIGURE 6. FALL TIME vs DELAY TIME
FIGURE 7. DISTORTION vs FREQUENCY FIGURE 8. POSITIVE SUPPLY CURRENT vs DELAY TIME
FIGURE 9. I
SUPPLY
+ vs V
SUPPLY
+ FIGURE 10. I
SUPPLY
- vs V
SUPPLY
-
Typical Performance Curves (Continued)
DELAY TIME (ns)
DELAY TIME (ns)
Vout = 1Vptp
DELAY TIME (ns)
3 Channels
X2 Low_0ns Delay
X2 Low_62ns Delay
X2 Hi_62ns Delay
X2 Hi_0ns Delay
X2 Low_0ns Delay
X2 Low_62ns Delay
X2 Hi_62ns Delay
X2 Hi_0ns Delay
EL9115
6
FN7441.7
January 12, 2012
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Typical Performance Curves (Continued)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
1.0
0.8
0.6
0.4
0.2
0
0 255075100 150
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
833mW
θ
J
A
=
1
5
0
°
C
/
W
Q
F
N
2
0
12585
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
θ
J
A
=
3
2
°C
/
W
Q
F
N
2
0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
FIGURE 13. EL9115 BLOCK DIAGRAM
+
+
+
+
+
+
DELAY LINE
DELAY LINE
DELAY LINE
18
TESTG
TESTB
TESTR
17
NSENABLE
SCLOCK
SDATA
X2
19
3
10
8
9
R_IN
G_IN
B_IN
CONTROL LOGIC
B_OUT
G_OUT
R_OUT
GND
GND
VSMO
VSM
51214
20
11
13
15
2
4
6
CENABLE
7
C
[BOTTOM PLATE]
VSPO
16
VSP
1
EL9115
P1-P3P4-P6P7-P9P10-P10

EL9115ILZ

Mfr. #:
Buy EL9115ILZ
Manufacturer:
Renesas / Intersil
Description:
Delay Lines / Timing Elements EL9115ILZ TRPL ANLOG G VID DELAY LINE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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