7
FN7441.7
January 12, 2012
Applications Information
EL9115 is a triple analog delay line receiver that allows skew
compensation between any three high frequency signals.
This part compensates for time skew introduced by a typical
CAT-5 cable with differing electrical lengths on each pair.
The EL9115 can be independently programmed via SPI
interface in steps of 2ns up to 62ns total delay on each
channel while achieving over 80MHz bandwidth.
Figure 13 shows the EL9115 block diagram. The three
analog inputs are ground reference single-ended signals.
After the signal is received, the delay is introduced by
switching filter blocks into the signal path. Each filter block is
an all-pass filter introducing 2ns delay. In addition to time
delay, each filter block also introduces some low pass
filtering. As a result, the bandwidth of the signal path
decreases from 120MHz at 0ns delay setting to 80MHz at
the maximum delay setting, as shown in Figure 1 of the
“Typical Performance Curves” on page 4.
In addition to delay, the extra amplifiers in the signal path
also introduce offset voltage. The output offset voltage can
shift by 100mV for X2 high setting and 50mV for X2 low.
In operation, it is best to allocate the most delayed signal
0ns delay and then increase the delay on the other channels
to bring them into line. This will result in the lowest power
and distortion solution to balancing delays.
Power Dissipation
As the delay setting increases, additional filter blocks turn on
and insert into the signal path. For each 2ns of delay per
channel, V
SP
current increases by 0.9mA while V
SM
does
not change significantly. Under the extreme settings, the
positive supply current reaches 140mA and the negative
supply current can be 35mA. Operating at ±5V power supply,
the total power dissipation is as shown in Equation 1:
θ
JA
required for long term reliable operation can be
calculated. This is done using Equation 2:
where:
T
J
is the maximum junction temperature (+135°C)
T
A
is the maximum ambient temperature (+85°C)
For a 20 Ld package in a proper layout PCB heat-sinking
copper area, 40°C/W θ
JA
thermal resistance can be
achieved. To disperse the heat, the bottom heat-spreader
must be soldered to the PCB. Heat flows through the
heat-spreader to the circuit board copper then spreads and
convects to air. Thus, the PCB copper plane becomes the
heatsink (see TB389). This has proven to be a very effective
technique. A separate application note, which details the
20 Ld QFN PCB design considerations, is available.
Serial Bus Operation
On the first negative clock edge after NSEnable goes low,
read the input from DATA (Figure 14). This DATA level
should be 0 (write into registers); READ is not supported.
Read the next two data bits on subsequent negative edges
and interpret them as the register to be filled. Reg 01 = R, 02
= G, 03 = B, 00 test use. Read the next five bits of data and
send them to register. At the end of each block of 8 bits, any
further data is treated as being a new word. Data entered is
PD 5 140mA 5 35mA• 875mW=+•=
(EQ. 1)
θ
JA
T
J
( T
A
) PD 57°=⁄ CW⁄–=
(EQ. 2)
TABLE 1. SERIAL BUS DATA
vwxyz DELAY
00000 0
00001 2
00010 4
00011 6
00100 8
00101 10
00110 12
00111 14
01000 16
01001 18
01010 20
01011 22
01100 24
01101 26
01110 28
01111 30
10000 32
10001 34
10010 36
10011 38
10100 40
10101 42
10110 44
10111 46
11000 48
11001 50
11010 52
11011 54
11100 56
11101 58
11110 60
11111 62
NOTE: Delay register word = 0abvwxyz; Red register - ab = 01;
Green register - ab = 10; Blue register - ab = 11; vwxyz selects delay.
EL9115
