[AK4101A]
MS0250-E-01 2012/11
- 19 -
Data Transmission Format
Data transmitted on the TX outputs is formatted in blocks as shown in
Figure 14. Each block consists of 192 frames. A
frame of data contains two sub-frames. A sub-frame consists of 32 bits of information. Each data bit received is coded
using a bi-phase mark encoding as a two binary state symbol. The preambles violate bi-phase encoding so they may be
differentiated from data. In bi-phase encoding, the first state of an input symbol is always the inverse of the last state of
the previous data symbol. For a logic “0”, the second state of the symbol is the same as the first state. For a “1”, the
second state is the opposite of the first.
Figure 15 illustrates a sample stream of 8 data bits encoded in 16 symbol states.
Frame 191 Frame 0 Frame 1
Sub-frame Sub-frame
M
Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2
Figure 14. Block format
0 1 1 0 0 0 1 0
Figure 15. A biphase-encoded bit stream
The sub-frame is defined in
Figure 16 below. Bits 0-3 of the sub-frame represent a preamble for synchronization. There
are three preambles. The block preamble, B, is contained in the first sub-frame of Frame 0. The channel 1 preamble, M,
is contained in the first sub-frame of all other frames. The channel 2 preamble, W, is contained in all of the second sub-
frames.
Table 6 below defines the symbol encoding for each of the preambles. Bits 4-27 of the sub-frame contain the 24 bit
audio sample in 2’s complement format with bit 27 as the most significant bit. For 16 bit mode, Bits 4-11 are all 0. Bit
28 is the validity flag. This is “H” if the audio sample is unreliable. Bit 29 is a user data bit. Frame 0 contains the first
bit of a 192 bit user data word. Frame 191 contains the last bit of the user data word. Bit 30 is a channel status bit.
Again frame 0 contains the first bit of the 192 bit word with the last bit in frame 191. Bit 31 is an even parity bit for bits
4-31 of the sub-frame.
Sync P
C
UV
L M
S Audio sample S
B B
0 3 4 27 28 29 30 31
Figure 16. Sub-frame format
The block of data contains consecutive frames transmitted at a state-bit rate of 64 times the sample frequency, fs. For
stereophonic audio, the left or A channel data is in channel 1 while the right or B data is in channel 2. For monophonic
audio, channel 1 contains the audio data.
Preamble Preceding state = 0 Preceding state = 1
B 11101000 00010111
M 11100010 00011101
W 11100100 00011011
Table 6. Sub-frame preamble encoding
[AK4101A]
MS0250-E-01 2012/11
- 20 -
Line Drivers
There are four RS422 line drivers on chip. The AES3 specification states that the line driver shall have a balanced
output with an internal impedance of 110 ohms ±20% and also requires a balanced output drive capability of 2 to 7
volts peak-to-peak into 110 ohm load. The internal impedance of the RS422 driver along with a series resistors of 56
ohms realizes this requirement. For consumer use(S/PDIF), the specifications require an output impedance of 75 ohms
±20% and a driver level of 0.5±20% volts peak to peak. A combination of 330 ohms in parallel with 100 ohms realizes
this requirement. The outputs can be set to ground by resetting the device or a software mute.
TXP
TXN
56 0.1u
XLR Connector
Transformer
Figure 17. Professional Output Driver Circuit
TXP
TXN
330 0.1u
RCA Phono
Connector
Transformer
100
Figure 18. Consumer Output Driver Circuit
[AK4101A]
MS0250-E-01 2012/11
- 21 -
Serial Control Interface
In asynchronous mode, four of the dual function pins become CSN, CCLK, CDTI and CDTO, a 4 wire microprocessor
interface. The internal 66 byte control register can then be read and written. The contents of the control register define,
in part, the mode of operation for the AK4101A.
Figure 19 illustrates the serial data flow associated with SCI read and
write operations. C1-0 bits are the chip address. The AK4101A looks for C1-0 bits to be a “11” before responding to
the incoming data. R/W is the Read/Write bit which is “0” for a read operation and “1” for a write operation. The
register address contained in A7-0 bits is decoded to select a particular byte of the control register. D7-0 bits on CDTI
pin is the control data coming from the microprocessor during a write operation. D7-0 bits on CDTO pin is the contents
of the addressed byte from the control register requested during a read operation. The address and data bits are framed
by CSN pin = “0”. During a write operation, each address and data bit is sampled on the rising edge of CCLK. During a
read operation, the address bits are sampled on the rising edge of CCLK while data on CDTO is output on the falling
edge of CCLK. CCLK has a maximum frequency of 5 MHz.
CDTI
CCLK
CSN
C1
0 1 2 3 4 5 6 7
16 17 18 19 20 21 22 23
D4 D5 D6D7** * * * C0 R/W D0D1 D2 D3
CDTO
Hi-Z (with pull-down resistor)
WRITE
CDTI
C1 D4 D5 D6D7** * * * C0 R/W D0D1 D2 D3
CDTO
Hi-Z (with pull-down resistor)
READ
D4 D5 D6D7 D0D1 D2 D3
Hi-Z
A7
8 9 101112131415
A1A2A3A4A5A6 A0
A7 A1A2A3A4A5A6 A0
“L”
C1-C0: Chip Address (Fixed to “11”)
R/W: READ/WRITE (0:READ, 1:WRITE)
*: Don’t care
A7-A0: Register Address
D7-D0: Control Data
Figure 19. Control I/F Timing
CSN
AK4101A
CCLK
CDTI
CDTO
CSN
AK4101A
CCLK
CDTI
CDTO
μ
P
CSN1
CCLK
CDTI
CDTO
CSN2
Figure 20. Typical connection with μP
Note: External pull-up resistor should not be attached to CDTO pins
since CDTO pin is internally connected to the pull-down resistor.

AK4101AVQ

Mfr. #:
Manufacturer:
Description:
IC TX RS422 QUAD 44LQFP
Lifecycle:
New from this manufacturer.
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