MAX5151ACPE Datasheet MAX5150BCEE+, MAX5150BEEE+, MAX5151AEEE+ | P10-P12

MSB LSB

MAX5150/MAX5151

puts become high impedance, and the serial inter-

face

remains active. Data in the input registers is

saved, allowing the MAX5150/MAX5151 to recall the

output state prior to entering shutdown when returning

to normal mode. Exit shutdown by recalling the previ-

ous condition or by updating the DAC with new infor-

mation. When returning to normal operation (exiting

shutdown), wait 20µs for output stabilization.

Serial Interface

The MAX5150/MAX5151 3-wire serial interface is com-

patible with both Microwire (Figure 2) and SPI/QSPI

(Figure 3) serial-interface standards. The 16-bit serial

input word consists of an address bit, two control bits,

and 13 bits of data (MSB to LSB) as shown in Figure 4.

Low-Power, Dual, 13-Bit Voltage-Output DACs

with Serial Interface

10 ______________________________________________________________________________________

16-BIT SERIAL WORD

FUNCTION

A0 C1 C0

D12.......................D0

(MSB) (LSB)

0 0 1 13-bit DAC data Load input register A; DAC registers are unchanged.

0 1 1 13-bit DAC data

Load all DAC registers from the shift register

(start up both DACs with new data.).

1 1 0 13-bit DAC data Load input register B; all DAC registers are updated.

0 1 0 13-bit DAC data Load input register A; all DAC registers are updated.

1 0 1 13-bit DAC data Load input register B; DAC registers are unchanged.

0 0 0 1 1 0 x xxxxxxxxx

Shut down DAC A (provided PDL = 1).

0 0 0 1 0 1 x xxxxxxxxx

Update DAC register B from input register B

(start up DAC B with data previously stored in input register B).

0 0 0 0 0 1 x xxxxxxxxx

Update DAC register A from input register A

(start up DAC A with data previously stored in input register A).

1 1 1 xxxxxxxxxxxxx

Shut down both DACs (provided PDL = 1).

1 0 0 xxxxxxxxxxxxx

Update both DAC registers from their respective input registers

(start up both DACs with data previously stored in the input registers).

0 0 0 1 1 1 x xxxxxxxxx

Shut down DAC B (provided PDL = 1).

0 0 0 0 1 0 x xxxxxxxxx UPO goes low (default).

0 0 0 0 1 1 x xxxxxxxxx UPO goes high.

0 0 0 1 0 0 1 xxxxxxxxx Mode 1, DOUT clocked out on SCLK’s rising edge.

0 0 0 1 0 0 0 xxxxxxxxx Mode 0, DOUT clocked out on SCLK’s falling edge (default).

0 0 0 0 0 0 x xxxxxxxxx No operation (NOP).

Table 1. Serial-Interface Programming Commands

x = Don’t care

Note: When A0, C1, and C0 = 0, then D12, D11, D10, and D9 become control bits.

SCLK

DIN

I/O

MAX5150

MAX5151

MICROWIRE

PORT

Figure 2. Connections for Microwire

The address and control bits determine the MAX5150/

MAX5151's response, as outlined in Table 1.

The MAX5150/MAX5151's digital inputs are double

buffered, which allows any of the following: loading the

input register(s) without updating the DAC register(s),

updating the DAC register(s) from the input register(s),

or updating the input and DAC registers concurrently.

The address and control bits allow the DACs to act

independently.

The 16-bit data can be sent as two 8-bit packets (SPI,

Microwire), with CS low during this period. The address

and control bits determine which register will be updat-

ed, and the state of the registers when exiting shut-

down. The 3-bit address/control determines the

following:

• registers to be updated

• clock edge on which data is to be clocked out via

the serial-data output (DOUT)

• state of the user-programmable logic output

• configuration of the device after shutdown.

The general timing diagram of Figure 5 illustrates how

data is acquired. Driving CS low enables the device to

receive data. Otherwise, the interface control circuitry is

disabled. With CS low, data at DIN is clocked into the

data is latched into the input and/or DAC registers

depending on the address and control bits. The maxi-

mum clock frequency guaranteed for proper operation

is 10MHz. Figure 6 depicts a more detailed timing dia-

gram of the serial interface.

MAX5150/MAX5151

Low-Power, Dual, 13-Bit Voltage-Output DACs

with Serial Interface

DIN

SCLK

MOSI

SCK

I/O

SPI/QSPI

PORT

+5V

CPOL = 0, CPHA = 0

MAX5150

MAX5151

Figure 3. Connections for SPI/QSPI

Figure 5. Serial-Interface Timing Diagram

SCLK

DIN

COMMAND

EXECUTED

A0 D0

D12

D11

D10

D9 D6 D5 D4 D3 D2 D1D8 D7

______________________________________________________________________________________ 11

MSB.......Data Bits.........LSB

D12.................................D0

13 Data Bits

16 Bits of Serial Data

Control Bits

C1, C0

Address Bits

MSB..................................................................................LSB

1 Address/2 Control Bits

Figure 4. Serial-Data Format

MAX5150/MAX5151

Low-Power, Dual, 13-Bit Voltage-Output DACs

with Serial Interface

12 ______________________________________________________________________________________

SCLK

DIN

CSO

CSS

CSW

CS1

CSH

Figure 6. Detailed Serial-Interface Timing Diagram

TO OTHER

SERIAL DEVICES

MAX5150

MAX5151

DIN

SCLK

MAX5150

MAX5151

MAX5150

MAX5151

DINDOUT DOUT DOUT

SCLK

DIN

SCLK

TO OTHER

SERIAL DEVICES

MAX5150

MAX5151

DIN

SCLK

MAX5150

MAX5151

DIN

SCLK

MAX5150

MAX5151

DIN

SCLK

DIN

SCLK

CS1

CS2

CS3

Figure 7. Daisy Chaining MAX5150/MAX5151s

Figure 8. Multiple MAX5150/MAX5151s Sharing a Common DIN Line

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MAX5151ACPE

Mfr. #:

Buy MAX5151ACPE

Manufacturer:

Maxim Integrated

Description:

Digital to Analog Converters - DAC Low-Power, Dual, 13-Bit Voltage-Output DACs in Small QSOP-16 Package

Lifecycle:

New from this manufacturer.

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MAX5151ACPE

MAX5151ACPE

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