USB375x
DS00001824A-page 18 2011 - 2014 Microchip Technology Inc.
During power-up and charger detection the USB Mux switches will be disabled regardless of the EnableMux1 and
EnableMux2 settings.
Once power-up and charger detection are complete EnableMux1 is enabled by default.
4.4 USB375x Registers
All registers are reset when VBUS goes below UVLO. All registers are accessed through the I
2
C interface defined below.
4.4.1 I
2
C INTERFACE
The SDA and SCL pins comprise the I
2
C interface of the USB375x. The I
2
C master controls all traffic to the USB375x.
If the USB375x has a change in status it can assert the INT_B by pulling this line to ground. The USB375x INT_B line
will stay low and then auto-clear after 1mS or until cleared by reading the Status Register. This prevents INT_B from
masking other interrupts if the line is shared with other I
2
C devices.
SCL, SDA, and INT_B will be tri-stated until VBUS is above the UVLO. VBUS must be present to operate the I
2
C inter-
face.
SCL is an input only pad. SDA is bi-directional and can be configured as an input or an open drain output during I
2
C
operations.
SDA, and INT_B are open collector when configured as an output. This requires an external pull-up resistor on SDA
and INT_B.
The USB375x-1 requires I
2
C communications in order for the default USB path to be enabled. By default, the 100mA
current limit is enabled. Only devices that draw <100mA will be enabled through the path as part of dead battery provi-
sion support. In order to bypass this limit, bits 0 (EnableOVP Switch) and 2 (OverideVBUS) in Register 1 (Configuration
Register) need to be set via I
2
C.
4.4.2 I
2
C REGISTER ACCESS
4.4.2.1 I
2
C Read Command
The slave supports two types of reads, single reads, and continuous reads. In a single read the master asserts a NACK
after the first read data. The format for a single read is shown in Figure 4-7. The read command has three phases. These
three phases are device address phase, register address phase, and read data phase. Each phase is terminated by an
ACK or NACK. The device address phase consists of the 7-bit slave address followed by a '1' to indicate a read. If the
address matches the slave's address then the slave drives an ACK. The register address phase consists of an 8-bit
register address. The slave will always ACK the register address. In the data phase the slave will return the register read
data. If the register address was a valid register than the slave will return the data, otherwise it will return 0xFF.
The continuous read command is similar to the single read command, however after the read data the master will drive
an ACK and then provide another register address. The master will then wait for the read data as shown in Figure 4-8.
The continuous read is terminated by the master by driving a NACK after the last read data and then asserting a STOP
condition.
FIGURE 4-7: I
2
C SINGLE READ
ACK Register Addr X7-bit Slave ID
R/W
7-bit Slave ID
ACK
R/W
P
P
Driven By
Master
Driven By
Slave
S
S
1
0
NACK
ACK
Register X Value
