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USB3751A-2-A4-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
2011 - 2014 Microchip Technology Inc. DS00001824A-page 19
USB375x
4.4.2.2 I
2
C Write Command
Similar to the read commands, the slave supports two types of write commands. The single write command is show in
Figure 4-9. The slave will always ACK the write data. Only the lower 4 bits of the register address are decoded. Writes
to undefined and read-only registers will be ignored.
The continuous write is shown in Figure 4-10. In this case after the ACK of the write data, the master will drive the next
register address. The continuous write will be terminated when the master asserts a STOP.
4.4.3 I
2
C ADDRESS
The default I
2
C address is 1101000. The two LSB are set by the OTP registers.
FIGURE 4-8: I
2
C CONTINUOUS READ
FIGURE 4-9: I
2
C SINGLE WRITE
FIGURE 4-10: I
2
C CONTINUOUS WRITE
TABLE 4-2: I
2
C ADDRESS
MSB LSB
110100
0
R/W
ACK
S
Register Addr [X]
ACK7-bit Slave ID
0
R/W
R/W
P
Driven By
Master
Driven By
Slave
P7-bit Slave ID
ACK
S
1
NACKRegister [X] Value
Register [X+1]
Value
ACK
P
R/W
Register [X] ValueACK Register X Addr7-bit Slave ID
Driven By
Master
Driven By
Slave
S 0 ACK ACK
ACK
S
Register Addr [X]
ACK7-bit Slave ID
0
R/W
R/W
P
Driven By
Master
Driven By
Slave
P7-bit Slave ID
ACK
S
1
NACKR e g is te r [X ] V a lu e
R e g is te r [X + 1 ]
Value
ACK
USB375x
DS00001824A-page 20 2011 - 2014 Microchip Technology Inc.
4.4.4 REG 0: STATUS REGISTER
This register indicates the current status of the USB375x.
.
4.4.5 REG 1: CONFIGURATION REGISTER
Field Name Bit Access Default Description
OVLO Status 0 rd 0 Over Voltage Lockout Comparator Status. Set to 0b
when VBUS goes above the OVLO threshold.
OVLO Latch 1 rd 0 Set to 1b when an unmasked OVLO interrupt occurs
on OVLO Status. Auto cleared when this register is
read.
OVP SwitchStatus 2 rd 0 Indicates the status of the OVP switch. A 0b indicates
the OVP switch is closed. A 1b indicates that the OVP
switch is open.
CurrentLimitStatus 3 rd 0 Indicates the status of the 100mA Current Limit. A 1b
indicates that the current limit is enabled.
ChrgDetComplete 4 rd 0 A 1b Indicates Charger Detection has completed.
ChargerType 7:5 rd 000 This register indicates the result of the automatic
charger detection.
000 = ChargerDetection is not complete
001 = DCP
010 = CDP
011 = SDP
100 = SE1 Low Current Charger
101 = SE1 High Current Charger
If EnhancedChrgDet = 0 the USB375x is unable to
distinguish between a DCP and a CDP and will return
DCP as the ChargerType.
Field Name Bit Access Default Description
EnableOVP Switch 0 r/w 0 The OVP switch will be enabled when this bit is set to
1b.
EnableCurrentLimit 1 r/w 0 Controls the 100mA current limit block. The 100mA
current limit will be enabled when this bit is set to 1b
and the OverrideCurrentLimit bit is also set to 1b.
OverideVBUS 2 r/w 0 When this bit is set to 1b the OVP switch is controlled
by the EnableOVP Switch bit.
OverrideCurrentLimit 3 r/w 0 When this bit is set to 1b the current limit is controlled
by the EnableCurrentLimit bit.
Reserved 4 r/w 0 Reserved
EnableMux1 5 r/w 1 When this bit is set to 1b the Mux 1 path is enabled
(USB3750 Only)
EnableMux2 6 r/w 0 When this bit is set to 1b the Mux 2 path is enabled
(USB3750 Only)
SoftPOR 7 r/w 0 Hardware reset. When this bit is set to 1b, the
USB375x will reset and restart the POR sequence.
This bit will autoclear in T
SOFT_POR
. The USB375x
registers should not be accessed until the T
SOFT_POR
time has expired.
2011 - 2014 Microchip Technology Inc. DS00001824A-page 21
USB375x
4.4.6 REG 2: BATTERY CHARGER REGISTER
These bits allow I
2
C control of the battery charger circuits. This will allow for custom defined charger detection algorithm
to be implemented. By default the I
2
C control bit is off and this register is under control of the charger detection state
machine. Once the charger detection state machine is complete the I
2
C master can set the I
2
C Control register to control
the charger detection circuits.
4.4.7 REG 3: BATTERY CHARGER STATUS REGISTER
Field Name Bit Access Default Description
SeRxEn 0 r/w 0 Single Ended Receiver Enable. Wen this bit is set to
1b the single ended receivers will be enabled
ContactDetectEn 1 r/w 0 Contact Detect Current Source Enable. When this bit
is set to 1b the I
DP_SRC current source shown in
Figure 4-3 will be enabled.
VdatSrcEn 2 r/w 0 Vdat voltage source enable. When this bit is set to 1b
the V
datSrc voltage source shown in Figure 4-3 will be
enabled.
HostChrgEn 3 r/w 0 When this bit is set to 1b, the charger detection
connections of DP and DM are swapped. The USB
signal path is not reversed. This is required when
differentiating between a Charging Downstream Port
(CDP) and a Dedicated Charging Port (DCP).
IdatSinkEn 4 r/w 0 Idat current sink enable. When this bit is set to 1b the
I
datSinkEn current source shown in Figure 4-3 will be
enabled.
DpPulldownEn 5 r/w 0 DP 15K pull down resistor enable. When this bit is set
to 1b the R
PD 15K pull down resistor on DP shown in
Figure 4-3 will be enabled.
DmPulldownEn 6 r/w 0 DM 15K pull down resistor enable. When this bit is set
to 1b the R
PD 15K pull down resistor on DM shown in
Figure 4-3 will be enabled.
I
2
C Control 7 r/w 0 When this bit is set to 0b the bits [6:0] are
disconnected from the Battery Charger circuits. When
this bit is set to 1b, bits [6:0] will control the charger
detection circuits.
Field Name Bit Access Default Description
VdatDet 0 rd 0 Indicates Vdat Det comparator output. A 1b indicates
that the VdatDet comparator shown in Figure 4-3 has
been tripped.
DpSeRx 1 rd 0 DP Single Ended Receiver Status. A 1b indicates that
the DP signal is above the V
SE_RX
threshold.
DmSeRx 2 rd 0 DM Single Ended Receiver Status. A 1b indicates that
the DM signal is above the V
SE_RX
threshold.
RxHiCurrent 3 rd 0 DM high current SE1 charger output. A 1b indicates
that the DM signal is above the V
SE_RXH
threshold.
Reserved 7:4 r 0000 Read Only.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

USB3751A-2-A4-TR

Mfr. #:
Buy USB3751A-2-A4-TR
Manufacturer:
Microchip Technology
Description:
USB Switch ICs USB2.0 PROTECT IC W/BATT CHG DETECT
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