XRT71D03IV-F Datasheet XRT71D03IV-F, XRT71D03IVTR-F | P4-P6

XRT71D03

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

PIN DESCRIPTIONS

PIN DESCRIPTION

AME

YPE

ESCRIPTION

AVDD ****

Analog Power Supply = 5V±5% or 3.3V±5%

GND ****

Digital Power Supply = 5V±5% or 3.3V±5%

RRCLK_0 O

Received Recovered Output (De-jittered) Clock - channel 0:

Output the de-jittered or smoothed clock if the jitter attenuator is enabled. The

de-jittered data, RRPOS/RRNEG are clocked to this signal.

If RRCLKES is “low”, RRPOS/RRNEG will be updated at the falling edge of

RRCLK.

If RRCLKES is “high”, RRPOS/RRNEG will be updated at the rising edge of

RRCLK.

RRPOS_0 O

Received Recovered Positive Data (De-Jittered) Output - channel

De-jittered positive data output. Updated on the rising or falling edge of

RRCLK, depending upon the state of the RRCLKES input pin (or bit-field set-

ting).

RRNEG_0 O

Received Recovered Negative Data (De-Jittered) Output - channel

De-jittered negative data output. Updated on the rising or falling edge of

RRCLK, depending upon the state of the RRCLKES input pin (or bit-field set-

ting).

RRCLKES I

Received Recovered Clock Edge Select Input:

Hardware Mode:

1. When RRCLKES = “0”, then RRPOS and RRNEG are updated on the fall-

ing edge of RRCLK

2. When RRCLKES = “1”, then RRPOS and RRNEG are updated on the rising

edge of RRCLK

OTE

This applies to all channels.

Host Mode

Connect this pin to GND when the 71D03 is configured in the Host Mode.

Internal 50 K Ohm pull-down resistor.

NC No Connection

Rest

Reset Input. (Active-Low):

A high-low transition will re-center the internal FIFO, and will clear the Com-

mand Registers (for Host Mode operation). Resetting this pin may corrupt data

within the device.

For normal operation, pull this pin to VDD.

Internal 50 K Ohm pull-up resistor.

DS3

/E3_1 I

DS3/E3 Select Input - channel 1:

This pin along with the STS-1 mode select pin selects the operating mode. The

following table provides the configuration:

STS-1

DS3

/E3

XRT71D04 Operating Mode

0 0 DS3 (44.736 MHz)

0 1 E3 (34.368 MHz)

1 0 STS-1 (51.84 MHz)

1 1 E3 (34.368 MHz)

Internal 50 K Ohm pull-down resistor.

VDD ****

Digital Power Supply = 5V±5% or 3.3V±5%

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XRT71D03

3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

MODE_CTRL I

Mode Control:

When “High” in Multimode, all channels are independent. When “Low”, the

Master Channel (channel0) controls DS3/E3_n, STS1_n, RCLKES, FSS and

MCLKn. DJA is NOT affected.

Internal 50 K Ohm pull-up resistor.

ICT

In Circuit Testing Input. (Active low):

With this pin tied to ground, all output pins will be in high impedance mode for

in-circuit-testing.

For normal operation this input pin should be tied to VDD.

Internal 50 K Ohm pull-up resistor.

HOST I

Host/Hardware Mode Select:

An active-high input enables the Host mode. Data is written to the command

registers to configure the XRT71D04.

In the Host mode, the states of discrete input pins are inactive.

An active-low input enables the Hardware Mode.In this mode, the discrete

inputs are active.

Internal 50 K Ohm pull-down resistor.

FLRST I

Fifo Limit Reset

Hardware Mode

Whenever the FIFO is within 2 bits of either underflow or overflow, the FLn) will

be set high.

This pin allows the user to reset the state of FL_n, (FIFO Limit) output pin.

This pin when pulsed “High”, resets the the FL_n output pin, (toggles to GND).

OTE

The FL_n could be set “High” again if the FIFO is within 2 bits of either

underflow or overflow.

Host Mode

Reading the FL_n bits in the status registers clears the FL_n pin. Master

RESET also clears the FL_n output.

This pin is tied to GND. FLRST has no effect in this mode.

Internal 50 K Ohm pull-down resistor.

GND ****

Digital Ground

NC No Connection

AGND ****

Analog Ground

FL_0 O

FIFO Limit - channel 0:

This output pin is driven high whenever the internal FIFO comes within two-bits

of being underflow or overflow.

STS1_0 I

SONET STS1 Mode Select - channel 0:

This pin along with the DS3/E3_0 select pin configures the XRT71D03 either in

E3, DS3 or STS-1 mode.

A table relating to the setting of the pins is given below:

STS-1

DS3

/E3

XRT71D03 Operating Mode

0 0 DS3 (44.736 MHz)

0 1 E3 (34.368 MHz)

1 0 STS-1 (51.84 MHz)

1 1 E3 (34.368 MHz)

This input pin is active only in the Hardware Mode

PIN DESCRIPTION

AME

YPE

ESCRIPTION

XRT71D03

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

DS3

/E3_0 I

DS3/E3 Select Input - channel 0:

See description pin 8.

Internal 50 K Ohm pull-down resistor.

DJA_0/SCLK I

Hardware Mode

Disable Jitter Attenuator Input - Channel 0:

An active-high disables the Jitter Attenuator. The RPOS/RNEG and RCLK will

be passed through without jitter attenuation.

Host Mode

Microprocessor Serial Interface Clock Signal:

This signal will be used to sample the data on the SDI pin, on the rising edge

of this signal. Additionally, during “Read” operations, the Microprocessor Serial

Interface will update the SDO output on the falling edge of this signal.

Internal 50 K Ohm pull-down resistor.

GND ****

Digital Ground

RPOS_2 I

Received Positive Data (Jittery) Input: - channel 2:

Data that is input on this pin is sampled on either the rising or falling edge of

RCLK depending on the setting of the RCLKES pin (pin 10).

If RCLKES is “high”, then RPOS will be sampled on the falling edge of RCLK.

If RCLKES is “low”, then RPOS will be sampled on the rising edge of RCLK.

Internal 50 K Ohm pull-up resistor.

RNEG_2 I

Received Negative Data (Jittery) - channel 2:

The input jittery negative data is sampled either on the rising or falling edge of

RCLK depending on the setting of RCLKES.

If RCLKES is “high”, then RNEG will be sampled on the falling edge of RCLK.

If RCLKES is “low”, then RPOS will be sampled on the rising edge of RCLK.

This pin is typically tied to the “RNEG” output pin of the LIU.

Internal 50 K Ohm pull-up resistor.

VDD ****

Digital Power Supply = 5V±5% or 3.3V±5%

RCLK_2 I

Received Clock (Jittery) - channel 2:

Clock input RCLK2 should be connected to the recovered clock.

Internal 50 K Ohm pull-up resistor.

GND ****

Digital Ground

MCLK_2 I

Master Clock Input - channel 2:

Reference clock for internal PLL. 44.736MHz+/-20ppm or 34.368MHz+/-

20ppm. This clock must be continuous and jitter free with duty cycle between

30 to 70%.

It is permissible to use the EXCLK signal orSTS1 clock.

Internal 50 K Ohm pull-up resistor.

DJA_2/CS I

Hardware Mode

Disable Jitter Attenuator Input - Channel 2:

See description of pin 25

Host Mode

Chip Select Input:

An active-low input enables the serial interface.

Internal 50 K Ohm pull-down resistor.

STS1_2 I

SONET STS1 Mode Select - channel 2:

See description pin 19

PIN DESCRIPTION

AME

YPE

ESCRIPTION

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

XRT71D03IV-F

Mfr. #:

Buy XRT71D03IV-F

Manufacturer:

MaxLinear

Description:

Clock Synthesizer / Jitter Cleaner 3 CH E3/DS3/STS-1 Jitter Attenuator

Lifecycle:

New from this manufacturer.

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XRT71D03IV-F

XRT71D03IV-F

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