TEF6892H/V2,557 Datasheet TEF6892H/V2,518, TEF6892H/V2,557, TEF6892H/V3,518 | P28-P30

2003 Oct 21 28

Philips Semiconductors Product speciﬁcation

Car radio integrated signal processor TEF6892H

Table 24 Description of data byte 10

Table 25 Description of data bits LBI[2:0] and PBI[2:0]

Table 26 Description of data bits ELB[1:0] and EPB[1:0]

11.2 Write mode

Table 27 Format for subaddress byte with default setting

BIT SYMBOL DESCRIPTION

7 to 5 GBC[3:1] Good block counter. Three least signiﬁcant bits of received valid blocks counter;

n = 0 to 62. Remark: the least signiﬁcant bit is not available for reading (assume

GBC0 = 0).

4 to 2 PBI[2:0] Previous block identiﬁcation. See Table 25.

1 and 0 EPB[1:0] Error status previous block. See Table 26.

LBI2 LBI1 LBI0

BLOCK TYPE IDENTIFICATION OF LAST AND PREVIOUS

RECEIVED BLOCK DATA

PBI2 PBI1 PBI0

000 A

001 B

010 C

011 D

100 C’

1 0 1 E (RBDS mode)

1 1 0 invalid E (RDS mode)

1 1 1 invalid block

ELB1 ELB0

ERROR STATUS OF LAST AND PREVIOUS RECEIVED BLOCK DATA

EPB1 EPB0

0 0 no errors

0 1 corrected burst error of maximum 2 bits

1 0 corrected burst error of maximum 5 bits

1 1 uncorrectable error

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

AIOF GATE SGAT SA4 SA3 SA2 SA1 SA0

− 00−−−−−

2003 Oct 21 29

Philips Semiconductors Product speciﬁcation

Car radio integrated signal processor TEF6892H

Table 28 Description of subaddress byte

Table 29 Selection of data byte

11.2.1 S

UBADDRESS 0H; RDS SETA

Table 30 Format of data byte 0H with default setting

BIT SYMBOL DESCRIPTION

7 AIOF Auto-increment off. 0 = auto-increment enabled; 1 = auto-increment disabled.

6GATEGate. 0=I

C-bus outputs (SDAG and SCLG) are controllable by the shortgate or the

autogate function; 1 = I

C-bus outputs are enabled.

5 SGAT Shortgate. 1=I

C-bus outputs (SDAG and SCLG) are enabled for a single

transmission following this control and disabled automatically.

4 to 0 SA[4:0] Data byte select. The subaddress value is auto-incremented when AIOF = 0 and will

revert from SA = 30 to SA = 0. SA = 31 can only be accessed via direct subaddress

selection, in which case auto-increment will revert from SA = 31 to SA = 0; see

Table 29.

SA4 SA3 SA2 SA1 SA0 HEX MNEMONIC ADDRESSED DATA BYTE

0 0 0 0 0 0 RDS SETA settings of RDS/RBDS

0 0 0 0 1 1 RDS SET B settings of RDS/RBDS

0 0 0 1 0 2 RDSCLK clock of RDS/RBDS

000113RDS

CONTROL

control of RDS/RBDS function

0 0 1 0 0 4 CONTROL control of supply and AF update

0 0 1 0 1 5 CSALIGN alignment of stereo channel separation

0 0 1 1 0 6 MULTIPATH control of weak signal sensitivity and timing

0 0 1 1 1 7 SNC alignment of SNC start and slope

0 1 0 0 0 8 HIGHCUT alignment of HCC start and slope

0 1 0 0 1 9 SOFTMUTE alignment soft mute start and slope

0 1 0 1 0 A RADIO control of radio functions

0 1 0 1 1 B INPUT/ASI source selector and ASI settings

0 1 1 0 0 C LOUDNESS loudness control

0 1 1 0 1 D VOLUME volume control

0 1 1 1 0 E TREBLE treble control

0 1 1 1 1 F BASS bass control

1 0 0 0 0 10 FADER fader control

1 0 0 0 1 11 BALANCE balance control

1 0 0 1 0 12 MIX control of output mixer

1 0 0 1 1 13 BEEP beep generator settings

1 1 1 1 1 1F AUTOGATE autogate control

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

− SYM1 SYM0 GBL5 GBL4 GBL3 GBL2 GBL1

00010001

2003 Oct 21 30

Philips Semiconductors Product speciﬁcation

Car radio integrated signal processor TEF6892H

Table 31 Description of data byte 0H

Table 32 Description of synchronization mode

11.2.2 S

UBADDRESS 1H; RDS SET B

Table 33 Format of data byte 1H with default setting

Table 34 Description of data byte 1H

11.2.3 S

UBADDRESS 2H; RDSCLK

Table 35 Format of data byte 2H with default setting

BIT SYMBOL DESCRIPTION

7 − Not used. Set to logic 0.

6 and 5 SYM[1:0] Synchronization mode. See Table 32.

4 to 0 GBL[5:1] Maximum good blocks lose (0 to 63). Number of valid blocks (good blocks counter) at

which both the good block counter and the bad block counter are reset to 0. Only used

when synchronized. GBL0 is located in byte RDS SET B.

When the bad block counter reaches value BBL (see byte RDS SET B) before the

good block counter reaches value GBL a new synchronization is started.

SYM1 SYM0 SYNCHRONIZATION MODE

0 0 no error correction; only error free blocks are handled as valid

0 1 limited error correction; up to 2 bits error correctable blocks are handled as valid

1 0 full error correction; up to 5 bits error correctable blocks are handled as valid

1 1 mixed mode; only error free blocks are handled as valid for synchronization search, but

when synchronized, up to 5 bits error correctable blocks are handled as valid

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

GBL0 RBDS BBL5 BBL4 BBL3 BBL2 BBL1 BBL0

00000001

BIT SYMBOL DESCRIPTION

7 GBL0 Maximum good blocks lose (0 to 63); see Table 31.

6 RBDS RBDS mode. 0 = RDS mode, RBDS type E blocks are handled as invalid (bad block);

1 = RBDS mode, RBDS type E blocks are handled as valid (good block).

5 to 0 BBL[5:0] Maximum bad blocks lose (0 to 63). Number of invalid blocks (bad blocks counter) at

which a new synchronization is started. Both the good block counter and the bad block

counter are reset to 0.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

−−TST3 TST2 TST1 TST0 CLKO CLKI

−−000001

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TEF6892H/V2,557

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NXP Semiconductors

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IC AUDIO TONE PROCESSOR 44PQFP

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TEF6892H/V2,557

TEF6892H/V2,557

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