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TEF6892H/V2,557

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59
2003 Oct 21 31
Philips Semiconductors Product specification
Car radio integrated signal processor TEF6892H
Table 36 Description of data byte 2H
Table 37 RDS clock description
11.2.4 SUBADDRESS 3H; RDS CONTROL
Table 38 Format of data byte 3H with default setting
Table 39 Description of data byte 3H
Table 40 Description of data available control
BIT SYMBOL DESCRIPTION
7 and 6 − Not used. Set to logic 0.
5 to 2 TST[3:0] Test. TST[3:0] = 0000: normal operation.
1 CLKO Clock input or output and buffered or unbuffered raw RDS output. See Table 37.
0 CLKI
CLKO CLKI RDS/RBDS CLOCK
0 0 RDS decoder mode; pin RDCL is disabled
0 1 for RDS decoder bypass mode; RDCL is burst clock input for raw RDS read-out
1 0 for RDS decoder mode: continuous block rate data available signal at pin RDCL;
for RDS decoder bypass mode: RDCL is clock output for raw RDS read-out
1 1 reserved
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DAC1 DAC0 NWSY BBG4 BBG3 BBG2 BBG1 BBG0
00000000
BIT SYMBOL DESCRIPTION
7 and 6 DAC[1:0] Data available control. See Table 40.
5 NWSY New synchronization search. 0 = synchronization is started by BBL value of bad block
counter only; 1 = restart of synchronization search. NWSY is automatically reset to
logic 0.
4 to 0 BBG[4:0] Maximum bad blocks gain. Number of invalid blocks (bad block counter) that is
allowed during synchronization search. If reached, a new synchronization is started.
BBG[4:0] = 0 disables this function.
DAC1 DAC0 DATA AVAILABLE CONTROL
0 0 standard output mode; new block data is signalled at every new received block
0 1 fast PI search mode; during synchronization search (SYNC = 0) A or C’ block data is
available and signalled, when synchronized standard output mode is active
1 0 reduced data request mode; when synchronized new block data is signalled every two
new received blocks
1 1 decoder bypass mode; raw RDS data from demodulator is available on pin RDDA
2003 Oct 21 32
Philips Semiconductors Product specification
Car radio integrated signal processor TEF6892H
11.2.5 SUBADDRESS 4H; CONTROL
Table 41 Format of data byte 4H with default setting
Table 42 Description of data byte 4H
11.2.6 SUBADDRESS 5H; CSALIGN
Table 43 Format of data byte 5H with default setting
Table 44 Description of data byte 5H
Table 45 FM stereo channel separation
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
STBR STBA AFUM AFUH RMUT − LETF ATTB
11000−00
BIT SYMBOL DESCRIPTION
7 STBR Standby mode RDS processing. 0 = RDS processing active; 1 = RDS processing in
standby mode (RDS off, RDS outputs LOW).
6 STBA Standby mode audio processing. 0 = audio processing active; 1 = audio processing
in standby mode (audio inputs and outputs at DC).
5 AFUM Enables AF update mute. 0 = AF update mute disabled; 1 = AF update mute enabled
(controlled by AFSAMP and AFHOLD input).
4 AFUH AF update hold function. 0 = disable, the weak signal processing hold is controlled by
the AFHOLD input only; 1 = hold. This is equal to taking the AFHOLD input LOW. The
bit is reset to 0, when AFHOLD input is set to LOW (i.e. at AF update or preset change).
3 RMUT Radio signal mute. 0 = no mute; 1 = mute with 1 ms ASI slope at start and stop.
2 − Not used. Set to logic 0.
1 LETF Fast level detector time constants. 0 = slow level detector time constants are used;
1 = fast level detector time constants are used. See Table 49.
0 ATTB Attack bound of the MPH and LEV detector. 0 = detectors are unbounded; 1 = range
of the MPH and LEV detector are limited in their range for immediate start of attack. In
AM mode the detectors are always unbounded.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CSR1 CSR0 CSA3 CSA2 CSA1 CSA0 −−
010111−−
BIT SYMBOL DESCRIPTION
7 and 6 CSR[1:0] FM stereo channel separation (high frequency). See Table 45.
5 to 2 CSA[3:0] FM stereo channel separation and adjustment. See Table 46.
1 and 0 − Not used. Set to logic 0.
CSR1 CSR0 FM STEREO CHANNEL SEPARATION (dB)
00 0
0 1 0.4
1 0 0.8
1 1 1.2
2003 Oct 21 33
Philips Semiconductors Product specification
Car radio integrated signal processor TEF6892H
Table 46 FM stereo channel separation and adjustment
11.2.7 S
UBADDRESS 6H; MULTIPATH
Table 47 Format of data byte 6H with default setting
Table 48 Description of data byte 6H
Table 49 Setting of the time constants of the LEVEL detector
Table 50 Setting of the time constants of the MPH detector (level, WAM and USN)
CSA3 CSA2 CSA1 CSA0
FM STEREO CHANNEL SEPARATION AND
ADJUSTMENT (dB)
0000 0
0001 0.2
:::: :
1110 2.8
1111 3.0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
USS1 USS0 WAS1 WAS0 LET1 LET0 MPT1 MPT0
01010000
BIT SYMBOL DESCRIPTION
7 and 6 USS[1:0] USN sensitivity for weak signal processing. See Fig.5.
5 and 4 WAS[1:0] WAM sensitivity for weak signal processing. See Fig.6.
3 and 2 LET[1:0] LEVEL detector time constant. See Table 49.
1 and 0 MPT[1:0] MPH detector time constants (level, WAM and USN). See Table 50.
LETF LET1 LET0
t
LEVEL
(s)
ATTACK DECAY
000 3 3
001 3 6
0 1 0 1.5 1.5
0 1 1 0.5 1.5
1 0 0 0.5 0.5
1 0 1 0.17 0.5
1 1 0 0.06 0.17
1 1 1 0.06 0.06
MPT1 MPT0
t
MPH
(s)
ATTACK DECAY
0 0 0.5 12
0 1 0.5 24
1 0 0.5 6
1 1 0.25 6
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59

TEF6892H/V2,557

Mfr. #:
Buy TEF6892H/V2,557
Manufacturer:
NXP Semiconductors
Description:
IC AUDIO TONE PROCESSOR 44PQFP
Lifecycle:
New from this manufacturer.
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