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HTF18C64_128_256x72D.fm - Rev. E 2/07 EN
13 ©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Register and PLL Specifications
Notes: 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM.
This is a subset of parameters for the specific PLL used. Detailed PLL information is available
in JEDEC standard JESD82.
Table 15: PLL Specifications
CU877 device or equivalent JESD82-8.01
Parameter Symbol Pins Condition Min Max Units
DC high-level input voltage
V
IH RESET# LVCMOS 0.65 × VDD –V
DC low-level input voltage
V
IL RESET# LVCMOS – 0.35 × VDD V
Input voltage (limits)
V
IN RESET#, CK, CK# –0.3 VDDQ + 0.3 V
DC high-level input voltage
V
IH CK, CK# Differential input 0.65 × VDD –V
DC low-level input voltage
V
IL CK, CK# Differential input – 0.35 × VDD V
Input differential-pair cross
voltage
V
IX CK, CK# Differential input (VDDQ/2) -
0.15
(VDDQ/2) +
0.15
V
Input differential voltage
V
ID(DC) CK, CK# Differential input 0.3 VDDQ + 0.4 V
Input differential voltage
V
ID(AC) CK, CK# Differential input 0.6 VDDQ + 0.4 V
Input current
I
I RESET# VI = VDDQ or VSSQ –10 10 µA
CK, CK# VI = VDDQ or VSSQ –250 250 µA
Output disabled current
I
ODL RESET# = VSSQ; VI = VIH(AC) or
VIL(DC)
100 – µA
Static supply current
I
DDLD CK = CK# = LOW – 500 µA
Dynamic supply
I
DD n/a CK, CK# = 270 MHz, all
outputs open
(not connected to PCB)
–300mA
Input capacitance
C
IN Each input VI = VDDQ or VSSQ23pF
Table 16: PLL Clock Driver Timing Requirements and Switching Characteristics
Parameter Symbol Min Max Units
Stabilization time
t
L–15µs
Input clock slew rate
t
LS
I
1.0 4 V/ns
SSC modulation frequency
30 33 kHz
SSC clock input frequency deviation
0.0 –0.50 %
PLL loop bandwidth (–3dB from unity gain)
2.0 – MHz
